stefan.raus 37238916df Testbenches: Unify and optimize HDL testbenches ... Create a common 'run_tb.sh' script to be called by every testbench. Unify file and testbenches names. Fix util_pack/cpack_tb. Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui) Add ascript for that generates output in xml format (used by CI tools).		2021-05-07 19:53:14 +03:00
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axi_read_slave.v	axi_dmac: tb: Allow testing asymmetric interface widths	2018-11-30 23:41:49 +02:00
axi_slave.v	axi_dmac: tb: Allow testing asymmetric interface widths	2018-11-30 23:41:49 +02:00
axi_write_slave.v	axi_dmac: tb: Allow testing asymmetric interface widths	2018-11-30 23:41:49 +02:00
dma_read_shutdown_tb	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_read_shutdown_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_read_tb	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_read_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_write_shutdown_tb	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_write_shutdown_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_write_tb	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
dma_write_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
regmap_tb	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
regmap_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
reset_manager_tb	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
reset_manager_tb.v	Testbenches: Unify and optimize HDL testbenches	2021-05-07 19:53:14 +03:00
tb_base.v	tb_base: Fix various test benches	2019-05-17 11:20:48 +03:00