4c51224696
Configure the maximum burst size as well as the maximum number of active requests on the AXI master interfaces according to the core configuration. This allows connected slaves to know what kind of requests to expect and allows them to configure themselves accordingly. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
#HDL Reference Designs
Analog Devices HDL libraries and projects
###Tools version:
- Xilinx : Vivado 2014.4.1
- Altera : Quartus 15.0
###Documentation and support
For first time users, it is highly recommended to go through our HDL user guide.
For support please visit our FPGA Reference Designs Support Community on EngineerZone.