56 lines
1.2 KiB
Verilog
Executable File
56 lines
1.2 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2019, 2020, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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reg clk = 1'b0;
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reg [3:0] reset_shift = 4'b1111;
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reg trigger_reset = 1'b0;
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wire reset;
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reg failed = 1'b0;
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reg sysref = 1'b0;
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initial
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begin
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$dumpfile (VCD_FILE);
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$dumpvars;
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`ifdef TIMEOUT
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#`TIMEOUT
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`else
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#100000
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`endif
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if (failed == 1'b0)
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$display("SUCCESS");
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else
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$display("FAILED");
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$finish;
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end
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initial forever #10 clk <= ~clk;
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always @(posedge clk) begin
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if (trigger_reset == 1'b1) begin
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reset_shift <= 3'b111;
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end else begin
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reset_shift <= {reset_shift[2:0],1'b0};
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end
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end
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assign reset = reset_shift[3];
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initial begin
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#1000;
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@(posedge clk) sysref <= 1'b1;
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@(posedge clk) sysref <= 1'b0;
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end
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task do_trigger_reset;
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begin
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@(posedge clk) trigger_reset <= 1'b1;
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@(posedge clk) trigger_reset <= 1'b0;
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end
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endtask
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