110 lines
4.2 KiB
Verilog
110 lines
4.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_jesd_align (
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// jesd interface
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rx_clk,
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rx_sof,
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rx_ip_data,
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rx_data);
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// jesd interface
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input rx_clk;
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input [ 3:0] rx_sof;
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input [31:0] rx_ip_data;
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// aligned data
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output [31:0] rx_data;
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// internal registers
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reg [ 3:0] rx_sof_hold = 'd0;
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reg [31:0] rx_ip_data_d = 'd0;
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reg [31:0] rx_data = 'd0;
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// internal signals
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wire [ 3:0] rx_sof_s;
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// dword may contain more than one frame per clock
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assign rx_sof_s = (rx_sof == 4'd0) ? rx_sof_hold : rx_sof;
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always @(posedge rx_clk) begin
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if (rx_sof != 4'd0) begin
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rx_sof_hold <= rx_sof;
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end
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rx_ip_data_d <= rx_ip_data;
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if (rx_sof_s[3] == 1'b1) begin
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rx_data[31:24] <= rx_ip_data[ 7: 0];
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rx_data[23:16] <= rx_ip_data[15: 8];
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rx_data[15: 8] <= rx_ip_data[23:16];
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rx_data[ 7: 0] <= rx_ip_data[31:24];
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end else if (rx_sof_s[2] == 1'b1) begin
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rx_data[31:24] <= rx_ip_data[31:24];
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rx_data[23:16] <= rx_ip_data_d[ 7: 0];
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rx_data[15: 8] <= rx_ip_data_d[15: 8];
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rx_data[ 7: 0] <= rx_ip_data_d[23:16];
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end else if (rx_sof_s[1] == 1'b1) begin
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rx_data[31:24] <= rx_ip_data[23:16];
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rx_data[23:16] <= rx_ip_data[31:24];
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rx_data[15: 8] <= rx_ip_data_d[ 7: 0];
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rx_data[ 7: 0] <= rx_ip_data_d[15: 8];
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end else if (rx_sof_s[0] == 1'b1) begin
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rx_data[31:24] <= rx_ip_data[15: 8];
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rx_data[23:16] <= rx_ip_data[23:16];
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rx_data[15: 8] <= rx_ip_data[31:24];
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rx_data[ 7: 0] <= rx_ip_data_d[ 7: 0];
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end else begin
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rx_data[31:24] <= 8'd0;
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rx_data[23:16] <= 8'd0;
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rx_data[15: 8] <= 8'd0;
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rx_data[ 7: 0] <= 8'd0;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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