Laszlo Nagy ae02773480 axi_dacfifo: Rewrote constraints to be more specific ... Some of the wildcards matched too many paths and disabled the timing checks on intraclock paths.		2018-04-11 15:09:54 +03:00
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Makefile	Make: Update makefiles	2017-11-20 14:27:39 +02:00
axi_dacfifo.v	axi_dacfifo: Major update and redesign	2017-08-22 09:16:21 +01:00
axi_dacfifo_address_buffer.v	axi_dacfifo: Major update and redesign	2017-08-22 09:16:21 +01:00
axi_dacfifo_constr.xdc	axi_dacfifo: Rewrote constraints to be more specific	2018-04-11 15:09:54 +03:00
axi_dacfifo_ip.tcl	axi_*: Infer clock and reset signals of an IP	2018-04-11 15:09:54 +03:00
axi_dacfifo_rd.v	axi_dacfifo: Major update and redesign	2017-08-22 09:16:21 +01:00
axi_dacfifo_wr.v	axi_dacfifo: Major update and redesign	2017-08-22 09:16:21 +01:00
util_dacfifo_bypass.v	[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx	2017-09-25 08:56:40 +01:00