215 lines
7.1 KiB
Tcl
215 lines
7.1 KiB
Tcl
## ***************************************************************************
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## ***************************************************************************
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## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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##
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## In this HDL repository, there are many different and unique modules, consisting
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## of various HDL (Verilog or VHDL) components. The individual modules are
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## developed independently, and may be accompanied by separate and unique license
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## terms.
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##
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## The user should read each of these license terms, and understand the
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## freedoms and responsibilities that he or she has by using this source/core.
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##
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## This core is distributed in the hope that it will be useful, but WITHOUT ANY
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## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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## A PARTICULAR PURPOSE.
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##
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## Redistribution and use of source or resulting binaries, with or without modification
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## of this file, are permitted under one of the following two license terms:
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##
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## 1. The GNU General Public License version 2 as published by the
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## Free Software Foundation, which can be found in the top level directory
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## of this repository (LICENSE_GPL2), and also online at:
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## <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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##
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## OR
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##
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## 2. An ADI specific BSD license, which can be found in the top level directory
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## of this repository (LICENSE_ADIBSD), and also on-line at:
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## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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## This will allow to generate bit files and not release the source code,
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## as long as it attaches to an ADI device.
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##
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## ***************************************************************************
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## ***************************************************************************
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# script name adi_make_boot_bin.tcl
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# -- HELP SECTION --
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#
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# This script was designed to work within the Xilinx tool command line interface
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# Script arguments:
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# 1 - xsa file location (default: ./system_top.xsa)
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# 2 - u-boot.elf file location/name (default: ./u-boot.elf)
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# 3 - build location (default: pwd: $PWD)"
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# 4 - bl31.elf(mp soc projects only) file location
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#
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# The order of script arguments is mandatory.
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#
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# Examples:
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# - adi_make_boot_bin.tcl
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# - adi_make_boot_bin.tcl $xsa_path/system_top.xsa $uboot_path/u-boot.elf
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# - adi_make_boot_bin.tcl $xsa_path/system_top.xsa $uboot_path/u-boot.elf $workspace
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# - adi_make_boot_bin.tcl $xsa_path/system_top.xsa $uboot_path/u-boot.elf $workspace $arm_trf_repo/bl31.elf
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set PWD [pwd]
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# init variables
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set app_type ""
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set xsa_file ""
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set uboot_file ""
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# getting parsed arguments
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set xsa_file [lindex $argv 0 ] ; # or .xsa(xilinx shell archive)
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set uboot_file [lindex $argv 1]
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set build_dir [lindex $argv 2]
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set arm_tr_frm_file [lindex $argv 3]
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# xsa file exists
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if { $xsa_file == "" } {
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set xsa_file system_top.xsa
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if { ![file exists $xsa_file] } {
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set xsa_file system_top.xsa
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}
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}
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if { ![file exists $xsa_file] } {
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puts "ERROR: xsa file location is not set nor located in $PWD"
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return
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}
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# uboot file exists
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if { $uboot_file == "" } {
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if {[catch {set uboot_file "[glob "./u-boot*.elf"]" } fid]} {
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puts stderr "ERROR: $fid\n\rNOTE: you must have a the u-boot.elf in [pwd]\n\
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\rSee: https://wiki.analog.com/resources/fpga/docs/build\n"
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}
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}
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if { ![file exists $uboot_file] } {
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puts "ERROR: uboot file location is not set, nor located in $PWD"
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return
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}
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# build dir defined
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if { $build_dir == "" } {
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set build_dir "boot_bin"
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}
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if { [file exists $build_dir] } {
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file delete -force $build_dir
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}
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catch { file mkdir $build_dir } err
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if { ![file exists $build_dir] } {
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puts "ERROR: Failed to create \"$build_dir\" dir"
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return
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}
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file copy -force $xsa_file $build_dir/system_top.xsa
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file copy -force $uboot_file $build_dir
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# Zynq MP arm trusted firwmware
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if { $app_type == "Zynq MP FSBL" } {
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if { $arm_tr_frm_file == "" } {
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set arm_tr_frm_file bl31.elf
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}
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if { ![file exists $arm_tr_frm_file] } {
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puts "ERROR: arm trusted firmware (bl31.el) file is not defined or located in $PWD"
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}
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}
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# get cpu(app_type)
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set cpu_name ""
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set app_type ""
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hsi open_hw_design $build_dir/system_top.xsa
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set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]
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if { $cpu_name == ""} {
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puts "ERROR: cpu name could not be determine from .xsa file"
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return
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} else {
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if { [regexp psu_cortexa53.. $cpu_name] } {
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set app_type "Zynq MP FSBL"
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} elseif { [regexp ps7_cortexa9.. $cpu_name] } {
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set app_type "Zynq FSBL"
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} elseif { $cpu_name == "sys_mb" } {
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puts "ERROR: boot_bin (first stage boot loader + ...) is design for arm processors"
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return
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} else {
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puts "ERROR: unknown processor \"$cpu_name\" detected in $build_dir/system_top.xsa"
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return
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}
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}
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# Zynq MP arm trusted firwmware
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if { $app_type == "Zynq MP FSBL" } {
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if { $arm_tr_frm_file == "" } {
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set arm_tr_frm_file bl31.elf
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}
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if { ![file exists $arm_tr_frm_file] } {
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puts "ERROR: arm trusted firmware (bl31.el) file is not defined or located in $PWD"
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} else {
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file copy -force $arm_tr_frm_file $build_dir
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}
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}
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puts "Using CPU $cpu_name"
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# create zynq.bif for target app
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set l_sq_bracket "\["
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set r_sq_bracket "\]"
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if { $app_type == "Zynq FSBL" } {
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set zynq_bif [open "$build_dir/zynq.bif" a+]
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puts $zynq_bif "the_ROM_image:"
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puts $zynq_bif "{"
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puts $zynq_bif "${l_sq_bracket}bootloader${r_sq_bracket} ./fsbl.elf"
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puts $zynq_bif "./system_top.bit"
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puts $zynq_bif "$uboot_file"
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puts $zynq_bif "}"
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close $zynq_bif
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} elseif { $app_type == "Zynq MP FSBL" } {
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set zynqmp_bif [open "$build_dir/zynqmp.bif" a+]
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puts $zynqmp_bif "the_ROM_image:"
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puts $zynqmp_bif "{"
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puts $zynqmp_bif "${l_sq_bracket}pmufw_image${r_sq_bracket} ./pmufw.elf"
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puts $zynqmp_bif "${l_sq_bracket}bootloader,destination_cpu=a53-0${r_sq_bracket} ./fsbl.elf"
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puts $zynqmp_bif "${l_sq_bracket}destination_device=pl${r_sq_bracket} ./system_top.bit"
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puts $zynqmp_bif "${l_sq_bracket}destination_cpu=a53-0,exception_level=el-3,trustzone${r_sq_bracket} $arm_tr_frm_file"
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puts $zynqmp_bif "${l_sq_bracket}destination_cpu=a53-0,exception_level=el-2${r_sq_bracket} $uboot_file"
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puts $zynqmp_bif "}"
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close $zynqmp_bif
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} else {
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puts "ERROR: unknown \"$app_type\" when creating zynqx.bif "
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return -level 0 -code error
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}
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# create fsbl_build.tcl script
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set fsbl_build [open "$build_dir/fsbl_build.tcl" a+]
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puts $fsbl_build "hsi open_hw_design system_top.xsa"
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puts $fsbl_build "platform create -name hw0 -hw system_top.xsa -os standalone -out ./output -proc $cpu_name"
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puts $fsbl_build "platform generate"
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close $fsbl_build
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cd $build_dir
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if {[catch { [exec xsct fsbl_build.tcl] } msg]} {
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puts "$msg"
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}
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puts "end of FSBL build"
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file copy -force output/hw0/export/hw0/sw/hw0/boot/fsbl.elf .
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if { $app_type == "Zynq FSBL" } {
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exec bootgen -image zynq.bif -w -o i BOOT.BIN
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} elseif { $app_type == "Zynq MP FSBL" } {
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file copy -force output/hw0/export/hw0/sw/hw0/boot/pmufw.elf .
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exec bootgen -image zynqmp.bif -arch zynqmp -o BOOT.BIN -w
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}
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puts "adi_make_boot_bin.tcl done: $build_dir/BOOT.BIN"
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## ***************************************************************************
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## ***************************************************************************
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