pluto_hdl_adi/projects/adv7511/ac701/system_top.v

200 lines
5.6 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
phy_reset_n,
phy_mdc,
phy_mdio,
phy_tx_clk,
phy_tx_ctrl,
phy_tx_data,
phy_rx_clk,
phy_rx_ctrl,
phy_rx_data,
fan_pwm,
gpio_lcd,
gpio_led,
gpio_sw,
iic_rstn,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
output phy_reset_n;
output phy_mdc;
inout phy_mdio;
output phy_tx_clk;
output phy_tx_ctrl;
output [ 3:0] phy_tx_data;
input phy_rx_clk;
input phy_rx_ctrl;
input [ 3:0] phy_rx_data;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [ 3:0] gpio_led;
inout [ 8:0] gpio_sw;
output iic_rstn;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
// assignments
assign mgt_clk_sel = 2'd0;
// instantiations
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.fan_pwm (fan_pwm),
.gpio_lcd_tri_io (gpio_lcd),
.gpio_led_tri_io (gpio_led),
.gpio_sw_tri_io (gpio_sw),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.iic_rstn (iic_rstn),
.mdio_io (phy_mdio),
.mdio_mdc (phy_mdc),
.phy_rst_n (phy_reset_n),
.rgmii_rd (phy_rx_data),
.rgmii_rx_ctl (phy_rx_ctrl),
.rgmii_rxc (phy_rx_clk),
.rgmii_td (phy_tx_data),
.rgmii_tx_ctl (phy_tx_ctrl),
.rgmii_txc (phy_tx_clk),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************