329 lines
8.4 KiB
Verilog
329 lines
8.4 KiB
Verilog
// ***************************************************************************
|
|
// ***************************************************************************
|
|
// Copyright 2011(c) Analog Devices, Inc.
|
|
//
|
|
// All rights reserved.
|
|
//
|
|
// Redistribution and use in source and binary forms, with or without modification,
|
|
// are permitted provided that the following conditions are met:
|
|
// - Redistributions of source code must retain the above copyright
|
|
// notice, this list of conditions and the following disclaimer.
|
|
// - Redistributions in binary form must reproduce the above copyright
|
|
// notice, this list of conditions and the following disclaimer in
|
|
// the documentation and/or other materials provided with the
|
|
// distribution.
|
|
// - Neither the name of Analog Devices, Inc. nor the names of its
|
|
// contributors may be used to endorse or promote products derived
|
|
// from this software without specific prior written permission.
|
|
// - The use of this software may or may not infringe the patent rights
|
|
// of one or more patent holders. This license does not release you
|
|
// from the requirement that you obtain separate licenses from these
|
|
// patent holders to use this software.
|
|
// - Use of the software either in source or binary form, must be run
|
|
// on or directly connected to an Analog Devices Inc. component.
|
|
//
|
|
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
|
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
|
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
//
|
|
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
|
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
|
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
|
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
|
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
|
|
`timescale 1ns/100ps
|
|
|
|
module system_top (
|
|
sys_rst,
|
|
sys_clk_p,
|
|
sys_clk_n,
|
|
|
|
uart_sin,
|
|
uart_sout,
|
|
|
|
ddr3_addr,
|
|
ddr3_ba,
|
|
ddr3_cas_n,
|
|
ddr3_ck_n,
|
|
ddr3_ck_p,
|
|
ddr3_cke,
|
|
ddr3_cs_n,
|
|
ddr3_dm,
|
|
ddr3_dq,
|
|
ddr3_dqs_n,
|
|
ddr3_dqs_p,
|
|
ddr3_odt,
|
|
ddr3_ras_n,
|
|
ddr3_reset_n,
|
|
ddr3_we_n,
|
|
|
|
sgmii_rxp,
|
|
sgmii_rxn,
|
|
sgmii_txp,
|
|
sgmii_txn,
|
|
|
|
phy_rstn,
|
|
mgt_clk_p,
|
|
mgt_clk_n,
|
|
mdio_mdc,
|
|
mdio_mdio,
|
|
|
|
fan_pwm,
|
|
|
|
gpio_lcd,
|
|
gpio_led,
|
|
gpio_sw,
|
|
|
|
iic_rstn,
|
|
iic_scl,
|
|
iic_sda,
|
|
|
|
hdmi_out_clk,
|
|
hdmi_hsync,
|
|
hdmi_vsync,
|
|
hdmi_data_e,
|
|
hdmi_data,
|
|
|
|
spdif,
|
|
|
|
rx_clk_in_p,
|
|
rx_clk_in_n,
|
|
rx_frame_in_p,
|
|
rx_frame_in_n,
|
|
rx_data_in_p,
|
|
rx_data_in_n,
|
|
|
|
tx_clk_out_p,
|
|
tx_clk_out_n,
|
|
tx_frame_out_p,
|
|
tx_frame_out_n,
|
|
tx_data_out_p,
|
|
tx_data_out_n,
|
|
|
|
gpio_txnrx,
|
|
gpio_enable,
|
|
gpio_resetb,
|
|
gpio_sync,
|
|
gpio_en_agc,
|
|
gpio_ctl,
|
|
gpio_status,
|
|
|
|
spi_csn,
|
|
spi_clk,
|
|
spi_mosi,
|
|
spi_miso
|
|
);
|
|
|
|
input sys_rst;
|
|
input sys_clk_p;
|
|
input sys_clk_n;
|
|
|
|
input uart_sin;
|
|
output uart_sout;
|
|
|
|
output [13:0] ddr3_addr;
|
|
output [ 2:0] ddr3_ba;
|
|
output ddr3_cas_n;
|
|
output [ 0:0] ddr3_ck_n;
|
|
output [ 0:0] ddr3_ck_p;
|
|
output [ 0:0] ddr3_cke;
|
|
output [ 0:0] ddr3_cs_n;
|
|
output [ 7:0] ddr3_dm;
|
|
inout [63:0] ddr3_dq;
|
|
inout [ 7:0] ddr3_dqs_n;
|
|
inout [ 7:0] ddr3_dqs_p;
|
|
output [ 0:0] ddr3_odt;
|
|
output ddr3_ras_n;
|
|
output ddr3_reset_n;
|
|
output ddr3_we_n;
|
|
|
|
input sgmii_rxp;
|
|
input sgmii_rxn;
|
|
output sgmii_txp;
|
|
output sgmii_txn;
|
|
|
|
output phy_rstn;
|
|
input mgt_clk_p;
|
|
input mgt_clk_n;
|
|
output mdio_mdc;
|
|
inout mdio_mdio;
|
|
|
|
output fan_pwm;
|
|
|
|
output [ 6:0] gpio_lcd;
|
|
output [ 7:0] gpio_led;
|
|
input [12:0] gpio_sw;
|
|
|
|
output iic_rstn;
|
|
inout iic_scl;
|
|
inout iic_sda;
|
|
|
|
output hdmi_out_clk;
|
|
output hdmi_hsync;
|
|
output hdmi_vsync;
|
|
output hdmi_data_e;
|
|
output [35:0] hdmi_data;
|
|
|
|
output spdif;
|
|
|
|
input rx_clk_in_p;
|
|
input rx_clk_in_n;
|
|
input rx_frame_in_p;
|
|
input rx_frame_in_n;
|
|
input [ 5:0] rx_data_in_p;
|
|
input [ 5:0] rx_data_in_n;
|
|
|
|
output tx_clk_out_p;
|
|
output tx_clk_out_n;
|
|
output tx_frame_out_p;
|
|
output tx_frame_out_n;
|
|
output [ 5:0] tx_data_out_p;
|
|
output [ 5:0] tx_data_out_n;
|
|
|
|
inout gpio_txnrx;
|
|
inout gpio_enable;
|
|
inout gpio_resetb;
|
|
inout gpio_sync;
|
|
inout gpio_en_agc;
|
|
inout [ 3:0] gpio_ctl;
|
|
inout [ 7:0] gpio_status;
|
|
|
|
output spi_csn;
|
|
output spi_clk;
|
|
output spi_mosi;
|
|
input spi_miso;
|
|
|
|
// internal signals
|
|
wire [16:0] gpio_i;
|
|
wire [16:0] gpio_o;
|
|
wire [16:0] gpio_t;
|
|
|
|
// instantiations
|
|
|
|
IOBUF i_iobuf_gpio_txnrx (
|
|
.I (gpio_o[16]),
|
|
.O (gpio_i[16]),
|
|
.T (gpio_t[16]),
|
|
.IO (gpio_txnrx));
|
|
|
|
IOBUF i_iobuf_gpio_enable (
|
|
.I (gpio_o[15]),
|
|
.O (gpio_i[15]),
|
|
.T (gpio_t[15]),
|
|
.IO (gpio_enable));
|
|
|
|
IOBUF i_iobuf_gpio_resetb (
|
|
.I (gpio_o[14]),
|
|
.O (gpio_i[14]),
|
|
.T (gpio_t[14]),
|
|
.IO (gpio_resetb));
|
|
|
|
IOBUF i_iobuf_gpio_sync (
|
|
.I (gpio_o[13]),
|
|
.O (gpio_i[13]),
|
|
.T (gpio_t[13]),
|
|
.IO (gpio_sync));
|
|
|
|
IOBUF i_iobuf_gpio_en_agc (
|
|
.I (gpio_o[12]),
|
|
.O (gpio_i[12]),
|
|
.T (gpio_t[12]),
|
|
.IO (gpio_en_agc));
|
|
|
|
genvar n;
|
|
generate
|
|
for (n = 0; n <= 3; n = n + 1) begin: g_iobuf_gpio_ctl
|
|
IOBUF i_iobuf_gpio_ctl (
|
|
.I (gpio_o[8+n]),
|
|
.O (gpio_i[8+n]),
|
|
.T (gpio_t[8+n]),
|
|
.IO (gpio_ctl[n]));
|
|
end
|
|
for (n = 0; n <= 7; n = n + 1) begin: g_iobuf_gpio_status
|
|
IOBUF i_iobuf_gpio_status (
|
|
.I (gpio_o[0+n]),
|
|
.O (gpio_i[0+n]),
|
|
.T (gpio_t[0+n]),
|
|
.IO (gpio_status[n]));
|
|
end
|
|
|
|
endgenerate
|
|
|
|
system_wrapper i_system_wrapper (
|
|
.ddr3_addr (ddr3_addr),
|
|
.ddr3_ba (ddr3_ba),
|
|
.ddr3_cas_n (ddr3_cas_n),
|
|
.ddr3_ck_n (ddr3_ck_n),
|
|
.ddr3_ck_p (ddr3_ck_p),
|
|
.ddr3_cke (ddr3_cke),
|
|
.ddr3_cs_n (ddr3_cs_n),
|
|
.ddr3_dm (ddr3_dm),
|
|
.ddr3_dq (ddr3_dq),
|
|
.ddr3_dqs_n (ddr3_dqs_n),
|
|
.ddr3_dqs_p (ddr3_dqs_p),
|
|
.ddr3_odt (ddr3_odt),
|
|
.ddr3_ras_n (ddr3_ras_n),
|
|
.ddr3_reset_n (ddr3_reset_n),
|
|
.ddr3_we_n (ddr3_we_n),
|
|
.fan_pwm (fan_pwm),
|
|
.gpio_lcd_tri_o (gpio_lcd),
|
|
.gpio_led_tri_o (gpio_led),
|
|
.gpio_sw_tri_i (gpio_sw),
|
|
.gpio_fmcomms2_i (gpio_i),
|
|
.gpio_fmcomms2_o (gpio_o),
|
|
.gpio_fmcomms2_t (gpio_t),
|
|
.hdmi_data (hdmi_data),
|
|
.hdmi_data_e (hdmi_data_e),
|
|
.hdmi_hsync (hdmi_hsync),
|
|
.hdmi_out_clk (hdmi_out_clk),
|
|
.hdmi_vsync (hdmi_vsync),
|
|
.iic_main_scl_io (iic_scl),
|
|
.iic_main_sda_io (iic_sda),
|
|
.iic_rstn (iic_rstn),
|
|
.mdio_mdc (mdio_mdc),
|
|
.mdio_mdio_io (mdio_mdio),
|
|
.mgt_clk_clk_n (mgt_clk_n),
|
|
.mgt_clk_clk_p (mgt_clk_p),
|
|
.phy_rstn (phy_rstn),
|
|
.sgmii_rxn (sgmii_rxn),
|
|
.sgmii_rxp (sgmii_rxp),
|
|
.sgmii_txn (sgmii_txn),
|
|
.sgmii_txp (sgmii_txp),
|
|
.spdif (spdif),
|
|
.sys_clk_n (sys_clk_n),
|
|
.sys_clk_p (sys_clk_p),
|
|
.sys_rst (sys_rst),
|
|
.spi_csn_i (1'b1),
|
|
.spi_csn_o (spi_csn),
|
|
.spi_miso_i (spi_miso),
|
|
.spi_mosi_i (1'b0),
|
|
.spi_mosi_o (spi_mosi),
|
|
.spi_sclk_i (1'b0),
|
|
.spi_sclk_o (spi_clk),
|
|
.rx_clk_in_n (rx_clk_in_n),
|
|
.rx_clk_in_p (rx_clk_in_p),
|
|
.rx_data_in_n (rx_data_in_n),
|
|
.rx_data_in_p (rx_data_in_p),
|
|
.rx_frame_in_n (rx_frame_in_n),
|
|
.rx_frame_in_p (rx_frame_in_p),
|
|
.tx_clk_out_n (tx_clk_out_n),
|
|
.tx_clk_out_p (tx_clk_out_p),
|
|
.tx_data_out_n (tx_data_out_n),
|
|
.tx_data_out_p (tx_data_out_p),
|
|
.tx_frame_out_n (tx_frame_out_n),
|
|
.tx_frame_out_p (tx_frame_out_p),
|
|
.uart_sin (uart_sin),
|
|
.uart_sout (uart_sout),
|
|
.unc_int4 (1'b0));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|