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pluto_hdl_adi/library/spi_engine/spi_axis_reorder
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Istvan Csomortani f86ae28e50 spi_engine/data_reorder: Initial commit 
In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.

The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
 		2021-10-18 16:13:31 +03:00
..
Makefile spi_engine/data_reorder: Initial commit 2021-10-18 16:13:31 +03:00
spi_axis_reorder.v spi_engine/data_reorder: Initial commit 2021-10-18 16:13:31 +03:00
spi_axis_reorder_ip.tcl spi_engine/data_reorder: Initial commit 2021-10-18 16:13:31 +03:00