Laszlo Nagy ddd8a14790 ad9081_fmca_ebz: Remove system reset from Xilinx PHY ... Reset in device clock domain caused timing failures. Since link reconfiguration is not supported the reset is not required.		2021-02-05 15:24:15 +02:00
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ad9081_fmca_ebz_bd.tcl	ad9081_fmca_ebz: Remove system reset from Xilinx PHY	2021-02-05 15:24:15 +02:00
ad9081_fmca_ebz_qsys.tcl	ad9081_fmca_ebz/a10soc: Np 12 support	2021-02-05 15:24:15 +02:00