701e5f6515
This will allow building base test harnesses and place on top of them existing block designs for simulation purposes. Test harnesses will contain basic functionality like - clock and reset generators - AXI master to aid register access of the cores. - memory model of the DDR - interrupt controller Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will connect to this harness as they do to a real base design. |
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| .. | ||
| adi_board.tcl | ||
| adi_env.tcl | ||
| adi_intel_msg.tcl | ||
| adi_make.tcl | ||
| adi_make_boot_bin.tcl | ||
| adi_pd.tcl | ||
| adi_project_intel.tcl | ||
| adi_project_xilinx.tcl | ||
| adi_tquest.tcl | ||
| adi_xilinx_msg.tcl | ||
| project-intel.mk | ||
| project-toplevel.mk | ||
| project-xilinx.mk | ||