Lars-Peter Clausen 8dc2161870 alt_mem_asym: Set read latency to 1 clock cycle ... In its default configuration the ram_2port module as a read latency of 2 clock cycles. Both the read address as well as the output data are registered. This is not the behavior that is expected from the alt_mem_asym module and causes incorrect behavior and data corruption in the util_adc_fifo. Disable the data output register to get a read latency of 1 clock cycle. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-08-13 10:28:11 +02:00
..
alt_mem_asym_hw.tcl	alt_mem_asym: Set read latency to 1 clock cycle	2017-08-13 10:28:11 +02:00