148 lines
4.5 KiB
Tcl
148 lines
4.5 KiB
Tcl
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proc init {cellpath otherInfo} {
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set ip [get_bd_cells $cellpath]
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bd::mark_propagate_override $ip \
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"ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ"
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bd::mark_propagate_only $ip \
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"DMA_AXI_ADDR_WIDTH"
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# On ZYNQ the core is most likely connected to the AXI3 HP ports so use AXI3
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# as the default.
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set family [string tolower [get_property FAMILY [get_property PART [current_project]]]]
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if {$family == "zynq"} {
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set axi_protocol 1
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} else {
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set axi_protocol 0
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}
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foreach dir {SRC DEST} {
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# This is a bit of a hack, but we can't change the protocol if the type
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# is not AXI MM
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set old [get_property "CONFIG.DMA_TYPE_${dir}" $ip]
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set_property "CONFIG.DMA_TYPE_${dir}" "0" $ip
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set_property "CONFIG.DMA_AXI_PROTOCOL_${dir}" $axi_protocol $ip
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set_property "CONFIG.DMA_TYPE_${dir}" $old $ip
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}
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}
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proc post_config_ip {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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# Update AXI interface properties according to configuration
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set max_bytes_per_burst [get_property "CONFIG.MAX_BYTES_PER_BURST" $ip]
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set fifo_size [get_property "CONFIG.FIFO_SIZE" $ip]
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foreach dir {"SRC" "DEST"} {
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set type [get_property "CONFIG.DMA_TYPE_$dir" $ip]
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if {$type != 0} {
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continue
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}
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set data_width [get_property "CONFIG.DMA_DATA_WIDTH_$dir" $ip]
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set max_beats_per_burst [expr {int(ceil($max_bytes_per_burst * 8.0 / $data_width))}]
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set intf [get_bd_intf_pins [format "%s/m_%s_axi" $cellpath [string tolower $dir]]]
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set_property CONFIG.MAX_BURST_LENGTH $max_beats_per_burst $intf
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# The core issues as many requests as the amount of data the FIFO can hold
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if {$dir == "SRC"} {
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set_property CONFIG.NUM_WRITE_OUTSTANDING 0 $intf
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set_property CONFIG.NUM_READ_OUTSTANDING $fifo_size $intf
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} else {
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set_property CONFIG.NUM_WRITE_OUTSTANDING $fifo_size $intf
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set_property CONFIG.NUM_READ_OUTSTANDING 0 $intf
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}
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}
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}
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proc axi_dmac_detect_async_clk { cellpath ip param_name clk_a clk_b } {
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set param_src [get_property "CONFIG.$param_name.VALUE_SRC" $ip]
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if {[string equal $param_src "USER"]} {
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return;
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}
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set clk_domain_a [get_property CONFIG.CLK_DOMAIN $clk_a]
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set clk_domain_b [get_property CONFIG.CLK_DOMAIN $clk_b]
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set clk_freq_a [get_property CONFIG.FREQ_HZ $clk_a]
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set clk_freq_b [get_property CONFIG.FREQ_HZ $clk_b]
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set clk_phase_a [get_property CONFIG.PHASE $clk_a]
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set clk_phase_b [get_property CONFIG.PHASE $clk_b]
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# Only mark it as sync if we can make sure that it is sync, if the
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# relationship of the clocks is unknown mark it as async
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if {$clk_domain_a != {} && $clk_domain_b != {} && \
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$clk_domain_a == $clk_domain_b && $clk_freq_a == $clk_freq_b && \
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$clk_phase_a == $clk_phase_b} {
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set clk_async 0
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} else {
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set clk_async 1
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}
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set_property "CONFIG.$param_name" $clk_async $ip
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# if {$clk_async == 0} {
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# bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are synchronous"
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# } else {
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# bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are asynchronous"
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# }
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}
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proc propagate {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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set src_type [get_property CONFIG.DMA_TYPE_SRC $ip]
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set dest_type [get_property CONFIG.DMA_TYPE_DEST $ip]
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set req_clk [get_bd_pins "$ip/s_axi_aclk"]
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if {$src_type == 2} {
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set src_clk [get_bd_pins "$ip/fifo_wr_clk"]
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} elseif {$src_type == 1} {
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set src_clk [get_bd_pins "$ip/s_axis_aclk"]
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} else {
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set src_clk [get_bd_pins "$ip/m_src_axi_aclk"]
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}
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if {$dest_type == 2} {
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set dest_clk [get_bd_pins "$ip/fifo_rd_clk"]
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} elseif {$dest_type == 1} {
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set dest_clk [get_bd_pins "$ip/m_axis_aclk"]
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} else {
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set dest_clk [get_bd_pins "$ip/m_dest_axi_aclk"]
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}
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axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_REQ_SRC" $req_clk $src_clk
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axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_SRC_DEST" $src_clk $dest_clk
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axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_DEST_REQ" $dest_clk $req_clk
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}
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proc post_propagate {cellpath otherinfo} {
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set ip [get_bd_cells $cellpath]
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set addr_width 16
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foreach dir {"SRC" "DEST"} {
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set type [get_property "CONFIG.DMA_TYPE_$dir" $ip]
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if {$type != 0} {
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continue
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}
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set intf [get_bd_intf_pins [format "%s/m_%s_axi" $cellpath [string tolower $dir]]]
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set addr_segs [get_bd_addr_segs -of_objects [get_bd_addr_spaces $intf]]
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if {$addr_segs != {}} {
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foreach addr_seg $addr_segs {
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set range [get_property "range" $addr_seg]
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set offset [get_property "offset" $addr_seg]
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set addr_width [expr max(round(log($range + $offset) / log(2)), $addr_width)]
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}
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} else {
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set addr_width 32
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}
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}
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set_property "CONFIG.DMA_AXI_ADDR_WIDTH" $addr_width $ip
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}
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