1d7a621567
When having multiple 936x in parallel, this change enables the use of source synchronous received clock from the master as sampling clock for other slaves. This will eliminate skew between the interfaces since the data delays are going to be tuned against the master clock after a multi-chip synchronization (MCS) is done. This eliminates the clock crossing from the slave to master domain inside the FPGA. |
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| .. | ||
| axi_ad9361_alt_lvds_rx.v | ||
| axi_ad9361_alt_lvds_tx.v | ||
| axi_ad9361_cmos_if.v | ||
| axi_ad9361_lvds_if.v | ||
| axi_ad9361_lvds_if_10.v | ||
| axi_ad9361_lvds_if_c5.v | ||