354 lines
10 KiB
Verilog
354 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_gpreg #(
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parameter integer ID = 0,
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parameter integer NUM_OF_IO = 8,
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parameter integer NUM_OF_CLK_MONS = 8,
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parameter integer BUF_ENABLE_0 = 1,
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parameter integer BUF_ENABLE_1 = 1,
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parameter integer BUF_ENABLE_2 = 1,
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parameter integer BUF_ENABLE_3 = 1,
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parameter integer BUF_ENABLE_4 = 1,
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parameter integer BUF_ENABLE_5 = 1,
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parameter integer BUF_ENABLE_6 = 1,
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parameter integer BUF_ENABLE_7 = 1)
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(
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// io
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output [ 31:0] up_gp_ioenb_0,
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output [ 31:0] up_gp_out_0,
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input [ 31:0] up_gp_in_0,
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output [ 31:0] up_gp_ioenb_1,
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output [ 31:0] up_gp_out_1,
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input [ 31:0] up_gp_in_1,
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output [ 31:0] up_gp_ioenb_2,
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output [ 31:0] up_gp_out_2,
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input [ 31:0] up_gp_in_2,
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output [ 31:0] up_gp_ioenb_3,
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output [ 31:0] up_gp_out_3,
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input [ 31:0] up_gp_in_3,
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output [ 31:0] up_gp_ioenb_4,
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output [ 31:0] up_gp_out_4,
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input [ 31:0] up_gp_in_4,
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output [ 31:0] up_gp_ioenb_5,
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output [ 31:0] up_gp_out_5,
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input [ 31:0] up_gp_in_5,
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output [ 31:0] up_gp_ioenb_6,
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output [ 31:0] up_gp_out_6,
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input [ 31:0] up_gp_in_6,
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output [ 31:0] up_gp_ioenb_7,
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output [ 31:0] up_gp_out_7,
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input [ 31:0] up_gp_in_7,
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// clock monitors
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input d_clk_0,
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input d_clk_1,
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input d_clk_2,
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input d_clk_3,
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input d_clk_4,
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input d_clk_5,
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input d_clk_6,
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input d_clk_7,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 15:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [ 31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 15:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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// version
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localparam [31:0] PCORE_VERSION = 32'h00040063;
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localparam integer BUF_ENABLE[7:0] = {BUF_ENABLE_7, BUF_ENABLE_6, BUF_ENABLE_5, BUF_ENABLE_4,
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BUF_ENABLE_3, BUF_ENABLE_2, BUF_ENABLE_1, BUF_ENABLE_0};
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// internal registers
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reg up_wack_d = 'd0;
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reg up_rack_d = 'd0;
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reg [ 31:0] up_rdata_d = 'd0;
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reg up_wack = 'd0;
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reg [ 31:0] up_scratch = 'd0;
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reg up_rack = 'd0;
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reg [ 31:0] up_rdata = 'd0;
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// internal signals
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wire up_rstn;
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wire up_clk;
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wire up_wreq;
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wire [ 13:0] up_waddr;
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wire [ 31:0] up_wdata;
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wire up_rreq;
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wire [ 13:0] up_raddr;
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wire up_wreq_s;
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wire up_rreq_s;
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wire [ 31:0] up_gp_ioenb_s[7:0];
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wire [ 31:0] up_gp_out_s[7:0];
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wire [ 31:0] up_gp_in_s[7:0];
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wire [ 7:0] d_clk_s;
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wire [ 16:0] up_wack_s;
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wire [ 16:0] up_rack_s;
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wire [ 31:0] up_rdata_s[16:0];
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// signal name changes
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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// split-up interfaces
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assign up_gp_ioenb_0 = up_gp_ioenb_s[0];
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assign up_gp_out_0 = up_gp_out_s[0];
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assign up_gp_in_s[0] = up_gp_in_0;
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assign up_gp_ioenb_1 = up_gp_ioenb_s[1];
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assign up_gp_out_1 = up_gp_out_s[1];
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assign up_gp_in_s[1] = up_gp_in_1;
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assign up_gp_ioenb_2 = up_gp_ioenb_s[2];
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assign up_gp_out_2 = up_gp_out_s[2];
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assign up_gp_in_s[2] = up_gp_in_2;
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assign up_gp_ioenb_3 = up_gp_ioenb_s[3];
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assign up_gp_out_3 = up_gp_out_s[3];
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assign up_gp_in_s[3] = up_gp_in_3;
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assign up_gp_ioenb_4 = up_gp_ioenb_s[4];
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assign up_gp_out_4 = up_gp_out_s[4];
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assign up_gp_in_s[4] = up_gp_in_4;
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assign up_gp_ioenb_5 = up_gp_ioenb_s[5];
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assign up_gp_out_5 = up_gp_out_s[5];
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assign up_gp_in_s[5] = up_gp_in_5;
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assign up_gp_ioenb_6 = up_gp_ioenb_s[6];
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assign up_gp_out_6 = up_gp_out_s[6];
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assign up_gp_in_s[6] = up_gp_in_6;
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assign up_gp_ioenb_7 = up_gp_ioenb_s[7];
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assign up_gp_out_7 = up_gp_out_s[7];
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assign up_gp_in_s[7] = up_gp_in_7;
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assign d_clk_s[0] = d_clk_0;
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assign d_clk_s[1] = d_clk_1;
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assign d_clk_s[2] = d_clk_2;
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assign d_clk_s[3] = d_clk_3;
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assign d_clk_s[4] = d_clk_4;
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assign d_clk_s[5] = d_clk_5;
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assign d_clk_s[6] = d_clk_6;
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assign d_clk_s[7] = d_clk_7;
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// up signals
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always @(posedge up_clk or negedge up_rstn) begin
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if (up_rstn == 1'b0) begin
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up_wack_d <= 1'd0;
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up_rack_d <= 1'd0;
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up_rdata_d <= 32'd0;
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end else begin
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up_wack_d <= | up_wack_s;
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up_rack_d <= | up_rack_s;
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up_rdata_d <= up_rdata_s[ 0] | up_rdata_s[ 1] | up_rdata_s[ 2] |
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up_rdata_s[ 3] | up_rdata_s[ 4] | up_rdata_s[ 5] | up_rdata_s[ 6] |
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up_rdata_s[ 7] | up_rdata_s[ 8] | up_rdata_s[ 9] | up_rdata_s[10] |
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up_rdata_s[11] | up_rdata_s[12] | up_rdata_s[13] | up_rdata_s[14] |
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up_rdata_s[15] | up_rdata_s[16];
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end
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end
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// generic register map
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assign up_wack_s[16] = up_wack;
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assign up_rack_s[16] = up_rack;
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assign up_rdata_s[16] = up_rdata;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00: up_rdata <= PCORE_VERSION;
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8'h01: up_rdata <= ID;
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8'h02: up_rdata <= up_scratch;
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// instantiations
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genvar n;
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generate
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// gpio
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if (NUM_OF_IO < 8) begin
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for (n = NUM_OF_IO; n < 8; n = n + 1) begin: g_unused_io
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assign up_gp_ioenb_s[n] = 32'd0;
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assign up_gp_out_s[n] = 32'd0;
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assign up_wack_s[n] = 1'd0;
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assign up_rdata_s[n] = 32'd0;
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assign up_rack_s[n] = 1'd0;
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end
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end
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for (n = 0; n < NUM_OF_IO; n = n + 1) begin: g_io
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axi_gpreg_io #(.ID (16+n)) i_gpreg_io (
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.up_gp_ioenb (up_gp_ioenb_s[n]),
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.up_gp_out (up_gp_out_s[n]),
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.up_gp_in (up_gp_in_s[n]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[n]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[n]),
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.up_rack (up_rack_s[n]));
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end
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// clock monitors
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if (NUM_OF_CLK_MONS < 8) begin
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for (n = NUM_OF_CLK_MONS; n < 8; n = n + 1) begin: g_unused_clock_mon
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assign up_wack_s[(8+n)] = 1'd0;
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assign up_rdata_s[(8+n)] = 32'd0;
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assign up_rack_s[(8+n)] = 1'd0;
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end
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end
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for (n = 0; n < NUM_OF_CLK_MONS; n = n + 1) begin: g_clock_mon
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axi_gpreg_clock_mon #(
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.ID (32+n),
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.BUF_ENABLE (BUF_ENABLE[n]))
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i_gpreg_clock_mon (
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.d_clk (d_clk_s[n]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[(8+n)]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[(8+n)]),
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.up_rack (up_rack_s[(8+n)]));
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end
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endgenerate
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_d),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_d),
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.up_rack (up_rack_d));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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