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Lars-Peter Clausen 516fb62b19 axi_dmac: Reset data stream resize blocks when disabled 
When the DMA controller gets disabled in the middle of a transfer it is
possible that the resize block contains a partial sample. Starting the next
transfer the partial sample will appear the begining of the new stream and
also cause a channel shift.

To avoid this make sure to reset and flush the resize blocks when the DMA
controller is disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2015-04-01 14:19:20 +02:00
library axi_dmac: Reset data stream resize blocks when disabled 2015-04-01 14:19:20 +02:00
projects projects/fmcomms2/c5soc: Add GPIO support. 2015-04-01 14:00:39 +03:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md README: Add tools version 2015-01-06 10:24:06 +02:00

README.md

hdl

Analog Devices HDL libraries and projects

Tools version:

  • Vivado 2014.2
  • Quartus 14.0

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga