114 lines
4.0 KiB
Tcl
114 lines
4.0 KiB
Tcl
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad713x_di
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create_bd_port -dir I ad713x_odr
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create_bd_port -dir O ad713x_sdpclk
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# create a SPI Engine architecture for the parallel data interface of AD713x
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# this design supports AD7132/AD7134/AD7136
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create_bd_cell -type hier dual_ad7134
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current_bd_instance /dual_ad7134
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I odr
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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if {$adc_resolution == 16 || $adc_resolution == 24} {
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set data_width 32
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} elseif {$adc_resolution == 32} {
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set data_width 64
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};
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_parameter execution CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_ip_instance axi_spi_engine axi
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ad_ip_parameter axi CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter axi CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter offload CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH $data_width
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ad_ip_parameter interconnect CONFIG.NUM_OF_SDI $adc_num_of_channels
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ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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ad_connect execution/spi m_spi
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ad_connect clk offload/spi_clk
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ad_connect clk offload/ctrl_clk
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ad_connect clk execution/clk
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ad_connect clk axi/s_axi_aclk
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ad_connect clk axi/spi_clk
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ad_connect clk interconnect/clk
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ad_connect axi/spi_resetn offload/spi_resetn
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ad_connect axi/spi_resetn execution/resetn
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ad_connect axi/spi_resetn interconnect/resetn
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ad_connect odr offload/trigger
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ad_connect resetn axi/s_axi_aresetn
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ad_connect irq axi/irq
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current_bd_instance /
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_ad7134_dma
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad7134_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad7134_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad7134_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $adc_num_of_channels]
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ad_ip_parameter axi_ad7134_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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# sdpclk clock generator - default clk0_out is 50 MHz
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ad_ip_instance axi_clkgen axi_sdp_clkgen
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ad_ip_parameter axi_sdp_clkgen CONFIG.CLKIN_PERIOD 10
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ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_MUL 12
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ad_ip_parameter axi_sdp_clkgen CONFIG.VCO_DIV 2
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ad_ip_parameter axi_sdp_clkgen CONFIG.CLK0_DIV 12
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ad_connect sys_cpu_clk dual_ad7134/clk
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ad_connect sys_cpu_clk axi_ad7134_dma/s_axis_aclk
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ad_connect sys_cpu_clk axi_sdp_clkgen/clk
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ad_connect sys_cpu_resetn dual_ad7134/resetn
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ad_connect sys_cpu_resetn axi_ad7134_dma/m_dest_axi_aresetn
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ad_connect dual_ad7134/m_spi ad713x_di
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ad_connect dual_ad7134/odr ad713x_odr
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ad_connect axi_ad7134_dma/s_axis dual_ad7134/M_AXIS_SAMPLE
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ad_connect ad713x_sdpclk axi_sdp_clkgen/clk_0
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ad_cpu_interconnect 0x44a00000 dual_ad7134/axi
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ad_cpu_interconnect 0x44a30000 axi_ad7134_dma
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ad_cpu_interconnect 0x44a40000 axi_sdp_clkgen
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad7134_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" dual_ad7134/irq
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad7134_dma/m_dest_axi
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