218 lines
6.4 KiB
Verilog
218 lines
6.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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input rx_ref_clk_p,
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input rx_ref_clk_n,
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input rx_sysref_p,
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input rx_sysref_n,
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output rx_sync_p,
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output rx_sync_n,
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input [ 3:0] rx_data_p,
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input [ 3:0] rx_data_n,
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input tx_ref_clk_p,
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input tx_ref_clk_n,
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input tx_sysref_p,
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input tx_sysref_n,
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input tx_sync_p,
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input tx_sync_n,
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output [ 3:0] tx_data_p,
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output [ 3:0] tx_data_n,
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input trig_p,
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input trig_n,
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inout adc_fdb,
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inout adc_fda,
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inout dac_irq,
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inout [ 1:0] clkd_status,
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inout adc_pd,
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inout dac_txen,
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output sysref_p,
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output sysref_n,
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output spi_csn_clk,
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output spi_csn_dac,
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output spi_csn_adc,
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output spi_clk,
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inout spi_sdio,
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output spi_dir);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [94:0] gpio_t;
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wire [20:0] gpio_bd;
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wire [ 2:0] spi_csn;
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wire spi_mosi;
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wire spi_miso;
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wire trig;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire tx_ref_clk;
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wire tx_sysref;
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wire tx_sync;
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// spi
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assign spi_csn_adc = spi_csn[2];
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assign spi_csn_dac = spi_csn[1];
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assign spi_csn_clk = spi_csn[0];
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// instantiations
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IBUFDS_GTE4 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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IBUFDS i_ibufds_rx_sysref (
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.I (rx_sysref_p),
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.IB (rx_sysref_n),
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.O (rx_sysref));
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OBUFDS i_obufds_rx_sync (
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.I (rx_sync),
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.O (rx_sync_p),
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.OB (rx_sync_n));
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IBUFDS_GTE4 i_ibufds_tx_ref_clk (
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.CEB (1'd0),
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.I (tx_ref_clk_p),
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.IB (tx_ref_clk_n),
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.O (tx_ref_clk),
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.ODIV2 ());
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IBUFDS i_ibufds_tx_sysref (
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.I (tx_sysref_p),
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.IB (tx_sysref_n),
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.O (tx_sysref));
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IBUFDS i_ibufds_tx_sync (
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.I (tx_sync_p),
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.IB (tx_sync_n),
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.O (tx_sync));
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daq3_spi i_spi (
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.spi_csn (spi_csn),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio),
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.spi_dir (spi_dir));
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OBUFDS i_obufds_sysref (
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.I (gpio_o[40]),
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.O (sysref_p),
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.OB (sysref_n));
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IBUFDS i_ibufds_trig (
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.I (trig_p),
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.IB (trig_n),
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.O (trig));
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assign gpio_i[94:40] = gpio_o[94:40];
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assign gpio_i[39] = trig;
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ad_iobuf #(.DATA_WIDTH(7)) i_iobuf (
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.dio_t (gpio_t[38:32]),
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.dio_i (gpio_o[38:32]),
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.dio_o (gpio_i[38:32]),
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.dio_p ({ adc_pd, // 38
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dac_txen, // 37
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adc_fdb, // 36
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adc_fda, // 35
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dac_irq, // 34
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clkd_status})); // 32
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assign gpio_i[31:21] = gpio_o[31:21];
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/* Board GPIOS. Buttons, LEDs, etc... */
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assign gpio_i[20: 8] = gpio_bd_i;
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assign gpio_bd_o = gpio_o[7:0];
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.rx_data_0_n (rx_data_n[0]),
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.rx_data_0_p (rx_data_p[0]),
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.rx_data_1_n (rx_data_n[1]),
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.rx_data_1_p (rx_data_p[1]),
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.rx_data_2_n (rx_data_n[2]),
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.rx_data_2_p (rx_data_p[2]),
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.rx_data_3_n (rx_data_n[3]),
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.rx_data_3_p (rx_data_p[3]),
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.rx_ref_clk_0 (rx_ref_clk),
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.rx_sync_0 (rx_sync),
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.rx_sysref_0 (rx_sysref),
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.spi0_csn (spi_csn),
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.spi0_miso (spi_miso),
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.spi0_mosi (spi_mosi),
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.spi0_sclk (spi_clk),
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.spi1_csn (),
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.spi1_miso (1'd0),
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.spi1_mosi (),
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.spi1_sclk (),
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.dac_fifo_bypass(gpio_o[41]),
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.tx_data_0_n (tx_data_n[0]),
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.tx_data_0_p (tx_data_p[0]),
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.tx_data_1_n (tx_data_n[1]),
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.tx_data_1_p (tx_data_p[1]),
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.tx_data_2_n (tx_data_n[2]),
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.tx_data_2_p (tx_data_p[2]),
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.tx_data_3_n (tx_data_n[3]),
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.tx_data_3_p (tx_data_p[3]),
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.tx_ref_clk_0 (tx_ref_clk),
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.tx_sync_0 (tx_sync),
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.tx_sysref_0 (tx_sysref));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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