326 lines
11 KiB
Verilog
326 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adrv9001_rx_channel #(
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parameter Q_OR_I_N = 0,
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parameter COMMON_ID = 0,
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parameter CHANNEL_ID = 0,
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parameter DISABLE = 0,
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parameter DATAFORMAT_DISABLE = 0,
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parameter DCFILTER_DISABLE = 0,
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parameter IQCORRECTION_DISABLE = 0,
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parameter DATA_WIDTH = 16
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) (
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// adc interface
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input adc_clk,
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input adc_rst,
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input adc_valid_in,
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input [(DATA_WIDTH-1):0] adc_data_in,
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output adc_valid_out,
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output [(DATA_WIDTH-1):0] adc_data_out,
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input [(DATA_WIDTH-1):0] adc_data_iq_in,
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output [(DATA_WIDTH-1):0] adc_data_iq_out,
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output adc_enable,
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input dac_valid_in,
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input [(DATA_WIDTH-1):0] dac_data_in,
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// channel interface
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output up_adc_pn_err,
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output up_adc_pn_oos,
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output up_adc_or,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack
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);
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localparam NUM_OF_SAMPLES = DATA_WIDTH/16;
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// internal signals
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wire [(NUM_OF_SAMPLES-1):0] adc_dfmt_valid_s;
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wire [(DATA_WIDTH-1):0] adc_dfmt_data_s;
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wire [(NUM_OF_SAMPLES-1):0] adc_dcfilter_valid_s;
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wire [(DATA_WIDTH-1):0] adc_dcfilter_data_s;
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wire [(NUM_OF_SAMPLES-1):0] adc_valid_out_s;
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wire adc_pn_err_s;
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wire adc_pn_oos_s;
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wire [3:0] adc_pnseq_sel;
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wire adc_dfmt_se_s;
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wire adc_dfmt_type_s;
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wire adc_dfmt_enable_s;
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wire adc_dcfilt_enb_s;
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wire [15:0] adc_dcfilt_offset_s;
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wire [15:0] adc_dcfilt_coeff_s;
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wire adc_iqcor_enb_s;
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wire [15:0] adc_iqcor_coeff_1_s;
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wire [15:0] adc_iqcor_coeff_2_s;
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wire [(DATA_WIDTH-1):0] adc_data_pn;
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wire [(DATA_WIDTH-1):0] pn7_data;
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wire [(DATA_WIDTH-1):0] pn15_data;
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wire [ 3:0] adc_data_sel_s;
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wire [15:0] adc_data_in_s;
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wire adc_valid_in_s;
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reg [15:0] full_ramp_counter = 'd0;
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reg adc_valid_in_d = 'h0;
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reg adc_valid_in_2d = 'h0;
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reg [(DATA_WIDTH-1):0] adc_data_in_d = 'h0;
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reg [(DATA_WIDTH-1):0] adc_data_in_2d = 'h0;
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reg dac_valid_in_d = 'h0;
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reg dac_valid_in_2d = 'h0;
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reg [(DATA_WIDTH-1):0] dac_data_in_d = 'h0;
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reg [(DATA_WIDTH-1):0] dac_data_in_2d = 'h0;
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// variables
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genvar n;
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// input pipeline stage to protect logic if data comes from an async clock domain
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always @(posedge adc_clk) begin
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adc_valid_in_d <= adc_valid_in;
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adc_valid_in_2d <= adc_valid_in_d;
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adc_data_in_d <= adc_data_in;
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adc_data_in_2d <= adc_data_in_d;
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end
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always @(posedge adc_clk) begin
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dac_valid_in_d <= dac_valid_in;
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dac_valid_in_2d <= dac_valid_in_d;
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dac_data_in_d <= dac_data_in;
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dac_data_in_2d <= dac_data_in_d;
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end
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assign adc_data_in_s = (adc_data_sel_s == 4'h0) ? adc_data_in_2d : dac_data_in_2d;
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assign adc_valid_in_s = (adc_data_sel_s == 4'h0) ? adc_valid_in_2d : dac_valid_in_2d;
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// iq correction inputs
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generate
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for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_datafmt
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if (DISABLE == 1 || DATAFORMAT_DISABLE == 1) begin
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assign adc_dfmt_valid_s[n] = adc_valid_in_s;
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assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in_s[((16*n)+15):(16*n)];
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end else begin
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ad_datafmt #(.DATA_WIDTH (16)) i_ad_datafmt (
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.clk (adc_clk),
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.valid (adc_valid_in_s),
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.data (adc_data_in_s[((16*n)+15):(16*n)]),
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.valid_out (adc_dfmt_valid_s[n]),
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.data_out (adc_dfmt_data_s[((16*n)+15):(16*n)]),
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.dfmt_enable (adc_dfmt_enable_s),
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.dfmt_type (adc_dfmt_type_s),
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.dfmt_se (adc_dfmt_se_s));
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end
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end
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for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_dcfilter
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if (DISABLE == 1 || DCFILTER_DISABLE == 1) begin
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assign adc_dcfilter_valid_s[n] = adc_dfmt_valid_s[n];
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assign adc_dcfilter_data_s[((16*n)+15):(16*n)] = adc_dfmt_data_s[((16*n)+15):(16*n)];
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end else begin
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ad_dcfilter i_ad_dcfilter (
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.clk (adc_clk),
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.valid (adc_dfmt_valid_s[n]),
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.data (adc_dfmt_data_s[((16*n)+15):(16*n)]),
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.valid_out (adc_dcfilter_valid_s[n]),
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.data_out (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
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.dcfilt_enb (adc_dcfilt_enb_s),
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.dcfilt_coeff (adc_dcfilt_coeff_s),
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.dcfilt_offset (adc_dcfilt_offset_s));
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end
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end
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assign adc_valid_out = adc_valid_out_s[0];
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assign adc_data_iq_out = adc_dcfilter_data_s;
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for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_iqcor
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if (DISABLE == 1 || IQCORRECTION_DISABLE == 1) begin
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assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n];
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assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)];
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end else begin
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ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
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.clk (adc_clk),
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.valid (adc_dcfilter_valid_s[n]),
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.data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
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.data_iq (adc_data_iq_in[((16*n)+15):(16*n)]),
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.valid_out (adc_valid_out_s[n]),
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.data_out (adc_data_out[((16*n)+15):(16*n)]),
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.iqcor_enable (adc_iqcor_enb_s),
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.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
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.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
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end
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end
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if (DISABLE == 1) begin
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assign adc_enable = 1'b0;
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assign up_adc_pn_err = 1'b0;
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assign up_adc_pn_oos = 1'b0;
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assign up_adc_or = 1'b0;
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assign up_wack = 1'b0;
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assign up_rdata = 32'b0;
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assign up_rack = 1'b0;
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end else begin
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// pn oos & pn err
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// PN7 x^7 + x^6 + 1
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ad_pngen #(
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.POL_MASK ( (1<<7) | (1<<6) ),
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.POL_W (7),
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.DW (16)
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) PN7_gen (
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.clk (adc_clk),
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.reset (adc_rst),
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.clk_en (adc_valid_in_s),
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.pn_init (adc_pn_oos_s),
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.pn_data_in (adc_data_in_s),
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.pn_data_out (pn7_data)
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);
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// PN15 x^15 + x^14 + 1
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ad_pngen #(
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.POL_MASK ( (1<<15) | (1<<14) ),
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.POL_W (15),
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.DW (16)
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) PN15_gen (
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.clk (adc_clk),
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.reset (adc_rst),
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.clk_en (adc_valid_in_s),
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.pn_init (adc_pn_oos_s),
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.pn_data_in (adc_data_in_s),
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.pn_data_out (pn15_data)
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);
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// reference nibble ramp and full ramp generator
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// next value is always the currently received value incremented
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always @(posedge adc_clk) begin
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if (adc_valid_in_s) begin
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full_ramp_counter <= adc_data_in_s + 16'd1;
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end
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end
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assign adc_data_pn = adc_pnseq_sel == 4'd4 ? pn7_data :
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adc_pnseq_sel == 4'd5 ? pn15_data :
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adc_pnseq_sel == 4'd10 ? {4{full_ramp_counter[3:0]}} :
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adc_pnseq_sel == 4'd11 ? full_ramp_counter : 'h0;
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assign valid_seq_sel = adc_pnseq_sel == 4'd4 || adc_pnseq_sel == 4'd5 ||
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adc_pnseq_sel == 4'd10 || adc_pnseq_sel == 4'd11;
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ad_pnmon #(
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.DATA_WIDTH (DATA_WIDTH),
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.OOS_THRESHOLD (8),
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.ALLOW_ZERO_MASKING(1)
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) i_pnmon (
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.adc_clk (adc_clk),
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.adc_valid_in (adc_valid_in_s),
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.adc_data_in (adc_data_in_s),
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.adc_data_pn (adc_data_pn),
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.adc_pattern_has_zero (adc_pnseq_sel[3]),
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.adc_pn_oos (adc_pn_oos_s),
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.adc_pn_err (adc_pn_err_s)
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);
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up_adc_channel #(
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.COMMON_ID (COMMON_ID),
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.CHANNEL_ID (CHANNEL_ID),
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.USERPORTS_DISABLE(1),
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.DATAFORMAT_DISABLE(DATAFORMAT_DISABLE),
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.DCFILTER_DISABLE(DCFILTER_DISABLE),
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.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE))
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i_up_adc_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_enable (adc_enable),
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.adc_iqcor_enb (adc_iqcor_enb_s),
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.adc_dcfilt_enb (adc_dcfilt_enb_s),
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.adc_dfmt_se (adc_dfmt_se_s),
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.adc_dfmt_type (adc_dfmt_type_s),
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.adc_dfmt_enable (adc_dfmt_enable_s),
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.adc_dcfilt_offset (adc_dcfilt_offset_s),
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.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
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.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
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.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
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.adc_pnseq_sel (adc_pnseq_sel),
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.adc_data_sel (adc_data_sel_s),
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.adc_pn_err (adc_pn_err_s & valid_seq_sel),
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.adc_pn_oos (adc_pn_oos_s & valid_seq_sel),
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.adc_or (1'd0),
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.up_adc_pn_err (up_adc_pn_err),
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.up_adc_pn_oos (up_adc_pn_oos),
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.up_adc_or (up_adc_or),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_decimation_m (),
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.up_usr_decimation_n (),
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.adc_usr_datatype_be (1'b0),
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.adc_usr_datatype_signed (1'b1),
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.adc_usr_datatype_shift (8'd0),
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.adc_usr_datatype_total_bits (8'd16),
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.adc_usr_datatype_bits (8'd16),
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.adc_usr_decimation_m (16'd1),
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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