106 lines
3.6 KiB
Verilog
106 lines
3.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module util_pulse_gen #(
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parameter PULSE_WIDTH = 7,
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parameter PULSE_PERIOD = 100000000)( // t_period * clk_freq
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input clk,
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input rstn,
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input [31:0] pulse_width,
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input [31:0] pulse_period,
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input load_config,
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output reg pulse,
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output [31:0] pulse_counter
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);
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// internal registers
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reg [31:0] pulse_period_cnt = 32'h0;
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reg [31:0] pulse_period_read = 32'b0;
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reg [31:0] pulse_width_read = 32'b0;
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reg [31:0] pulse_period_d = 32'b0;
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reg [31:0] pulse_width_d = 32'b0;
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// flop the desired period
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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pulse_period_d <= PULSE_PERIOD;
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pulse_width_d <= PULSE_WIDTH;
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pulse_period_read <= PULSE_PERIOD;
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pulse_width_read <= PULSE_WIDTH;
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end else begin
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// latch the input period/width values
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if (load_config) begin
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pulse_period_read <= pulse_period;
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pulse_width_read <= pulse_width;
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end
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// update the current period/width at the end of the period
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if (pulse_period_cnt == 32'h1) begin
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pulse_period_d <= pulse_period_read;
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pulse_width_d <= pulse_width_read;
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end
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end
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end
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// a free running counter
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always @(posedge clk) begin
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if (pulse_period_cnt == 'b0) begin
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pulse_period_cnt <= pulse_period_d;
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end else begin
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pulse_period_cnt <= pulse_period_cnt - 32'b1;
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end
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end
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// generate pulse with a specified width
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always @ (posedge clk) begin
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if ((pulse_period_cnt == 'h0) || (rstn == 1'b0)) begin
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pulse <= 1'b0;
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end else if (pulse_period_cnt == pulse_width_d) begin
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pulse <= 1'b1;
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end
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end
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assign pulse_counter = pulse_period_cnt;
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endmodule
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