140 lines
5.6 KiB
Tcl
140 lines
5.6 KiB
Tcl
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package require qsys 14.0
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_intel.tcl
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ad_ip_create avl_dacfifo {Avalon DDR DAC Fifo} p_avl_dacfifo_elab
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ad_ip_files avl_dacfifo [list\
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$ad_hdl_dir/library/common/util_delay.v \
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$ad_hdl_dir/library/common/ad_b2g.v \
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$ad_hdl_dir/library/common/ad_g2b.v \
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$ad_hdl_dir/library/common/ad_mem.v \
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util_dacfifo_bypass.v \
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avl_dacfifo_wr.v \
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avl_dacfifo_rd.v \
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avl_dacfifo.v \
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avl_dacfifo_constr.sdc]
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter DAC_DATA_WIDTH INTEGER 64
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ad_ip_parameter DAC_MEM_ADDRESS_WIDTH INTEGER 8
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ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
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ad_ip_parameter DMA_MEM_ADDRESS_WIDTH INTEGER 8
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ad_ip_parameter AVL_DATA_WIDTH INTEGER 512
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ad_ip_parameter AVL_ADDRESS_WIDTH INTEGER 25
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ad_ip_parameter AVL_BURST_LENGTH INTEGER 127
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ad_ip_parameter AVL_BASE_ADDRESS INTEGER 0
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ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x800000
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# interfaces
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ad_interface clock dma_clk input 1 clk
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ad_interface reset dma_rst input 1 if_dma_clk
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ad_interface signal dma_xfer_req input 1 xfer_req
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add_interface s_axis axi4stream end
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set_interface_property s_axis associatedClock if_dma_clk
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set_interface_property s_axis associatedReset if_dma_rst
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add_interface_port s_axis dma_valid tvalid Input 1
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add_interface_port s_axis dma_xfer_last tlast Input 1
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add_interface_port s_axis dma_ready tready Output 1
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add_interface_port s_axis dma_data tdata Input DMA_DATA_WIDTH
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ad_interface clock dac_clk input 1 clk
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ad_interface reset dac_rst input 1 if_dac_clk
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ad_interface signal dac_valid input 1 valid
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ad_interface signal dac_data output DAC_DATA_WIDTH data
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ad_interface signal dac_dunf output 1 unf
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ad_interface signal dac_xfer_out output 1 xfer_out
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ad_interface signal bypass input 1 bypass
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add_interface avl_clock clock end
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add_interface_port avl_clock avl_clk clk input 1
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add_interface avl_reset reset end
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set_interface_property avl_reset associatedclock avl_clock
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add_interface_port avl_reset avl_reset reset input 1
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add_interface amm_ddr avalon master
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add_interface_port amm_ddr avl_address address output 25
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add_interface_port amm_ddr avl_burstcount burstcount output 7
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add_interface_port amm_ddr avl_byteenable byteenable output 64
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add_interface_port amm_ddr avl_read read output 1
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add_interface_port amm_ddr avl_readdata readdata input 512
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add_interface_port amm_ddr avl_readdata_valid readdatavalid input 1
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add_interface_port amm_ddr avl_ready waitrequest_n input 1
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add_interface_port amm_ddr avl_write write output 1
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add_interface_port amm_ddr avl_writedata writedata output 512
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set_interface_property amm_ddr associatedClock avl_clock
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set_interface_property amm_ddr associatedReset avl_reset
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set_interface_property amm_ddr addressUnits WORDS
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# elaborate
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proc p_avl_dacfifo_elab {} {
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# read parameters
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set m_device_family [get_parameter_value "DEVICE_FAMILY"]
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set m_dma_data_width [get_parameter_value "DMA_DATA_WIDTH"]
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set m_dma_mem_addr_width [get_parameter_value "DMA_MEM_ADDRESS_WIDTH"]
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set m_avl_data_width [get_parameter_value "AVL_DATA_WIDTH"]
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set m_avl_addr_width [get_parameter_value "AVL_ADDRESS_WIDTH"]
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set m_dac_data_width [get_parameter_value "DAC_DATA_WIDTH"]
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set m_dac_mem_addr_width [get_parameter_value "DAC_MEM_ADDRESS_WIDTH"]
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set m_dac_mem_addr_width_bypass 10
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if {$m_dma_data_width > $m_dac_data_width} {
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set m_dma_to_dac_ratio [expr $m_dma_data_width/$m_dac_data_width]
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if {$m_dma_to_dac_ratio eq 2} {
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set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 1]
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} elseif {$m_dma_to_dac_ratio eq 4} {
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set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 2]
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} else {
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set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 3]
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}
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} else {
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set m_dma_to_dac_ratio [expr $m_dac_data_width/$m_dma_data_width]
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if {$m_dma_to_dac_ratio eq 1} {
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set m_dma_mem_addr_width_bypass $m_dac_mem_addr_width_bypass
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} elseif {$m_dma_to_dac_ratio eq 2} {
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set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 1]
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} elseif {$m_dma_to_dac_ratio eq 4} {
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set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 2]
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} else {
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set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 3]
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}
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}
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# intel memory for WRITE side
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add_hdl_instance ad_mem_asym_wr intel_mem_asym 1.0
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set_instance_parameter_value ad_mem_asym_wr DEVICE_FAMILY $m_device_family
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set_instance_parameter_value ad_mem_asym_wr A_ADDRESS_WIDTH $m_dma_mem_addr_width
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set_instance_parameter_value ad_mem_asym_wr A_DATA_WIDTH $m_dma_data_width
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set_instance_parameter_value ad_mem_asym_wr B_DATA_WIDTH $m_avl_data_width
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# intel memory for READ side
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add_hdl_instance ad_mem_asym_rd intel_mem_asym 1.0
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set_instance_parameter_value ad_mem_asym_rd DEVICE_FAMILY $m_device_family
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set_instance_parameter_value ad_mem_asym_rd A_ADDRESS_WIDTH 0
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set_instance_parameter_value ad_mem_asym_rd A_DATA_WIDTH $m_avl_data_width
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set_instance_parameter_value ad_mem_asym_rd B_ADDRESS_WIDTH $m_dac_mem_addr_width
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set_instance_parameter_value ad_mem_asym_rd B_DATA_WIDTH $m_dac_data_width
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# intel memory for bypass logic
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add_hdl_instance ad_mem_asym_bypass intel_mem_asym 1.0
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set_instance_parameter_value ad_mem_asym_bypass DEVICE_FAMILY $m_device_family
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set_instance_parameter_value ad_mem_asym_bypass A_ADDRESS_WIDTH $m_dma_mem_addr_width_bypass
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set_instance_parameter_value ad_mem_asym_bypass A_DATA_WIDTH $m_dma_data_width
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set_instance_parameter_value ad_mem_asym_bypass B_ADDRESS_WIDTH $m_dac_mem_addr_width_bypass
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set_instance_parameter_value ad_mem_asym_bypass B_DATA_WIDTH $m_dac_data_width
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}
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