ee56db8d50
tcl: FCLK2 was modified from 100 MHz to 125 MHz. xdc: rx_clk period constraint was redefined from 8ns (125 MHz) to 4ns (250 MHz) |
||
---|---|---|
.. | ||
common | ||
zc706 |
ee56db8d50
tcl: FCLK2 was modified from 100 MHz to 125 MHz. xdc: rx_clk period constraint was redefined from 8ns (125 MHz) to 4ns (250 MHz) |
||
---|---|---|
.. | ||
common | ||
zc706 |