318dcbb5d9
The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default. The OUTCLK frequency is the same as the REFCLK. The main reason of this modification is that the links should come up without any DPR access, after power up, using the default reference clock configuration (122.88 MHz). |
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a10gx | ||
a10soc | ||
common | ||
kcu105 | ||
zc706 | ||
zcu102 | ||
Makefile |