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Liviu.Iacob 5350baffd0 adrv9009zu11eg/common/adrv9009zu11eg_bd: Add logic for TX_JESD_L=4 2022-10-03 10:27:33 +03:00
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ad40xx_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad469x_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad719x_asdz ad719x_asdz/coraz7s: Initial commit 2022-09-28 16:30:42 +03:00
ad738x_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad777x_ardz scripts:adi_env: Change the default version of Quartus Standard to 21.1 (#996) 2022-08-24 17:01:06 +03:00
ad4630_fmc ad4630_fmc: Match project name with folder name 2022-09-26 15:37:49 +03:00
ad5758_sdz scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad5766_sdz scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad6676evb scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad7134_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad7405_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad7616_sdz scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad7768evb Added axi_ad7768 IP Core (#989) 2022-08-24 16:57:14 +03:00
ad9081_fmca_ebz projects: starndadize the jesd make parameters 2022-09-13 11:53:21 +03:00
ad9082_fmca_ebz projects: starndadize the jesd make parameters 2022-09-13 11:53:21 +03:00
ad9083_evb scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad9208_dual_ebz projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
ad9213_dual_ebz scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad9265_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad9434_fmc projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
ad9467_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad9656_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad9695_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad9739a_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad9783_ebz ad9783_ebz: Match project name with folder name 2022-09-26 15:37:49 +03:00
ad77681evb scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad_fmclidar1_ebz scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
ad_quadmxfe1_ebz projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
adaq7980_sdz scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
adaq8092_fmc scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
adrv9001 scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
adrv9009 adrv9009/common/adrv9009_bd: Add logic for TX_JESD_L=2 2022-10-03 10:27:33 +03:00
adrv9009zu11eg adrv9009zu11eg/common/adrv9009zu11eg_bd: Add logic for TX_JESD_L=4 2022-10-03 10:27:33 +03:00
adrv9361z7035 scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
adrv9364z7020 scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
adrv9371x projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
adv7511 scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
adv7513 scripts:adi_env: Change the default version of Quartus Standard to 21.1 (#996) 2022-08-24 17:01:06 +03:00
arradio scripts:adi_env: Change the default version of Quartus Standard to 21.1 (#996) 2022-08-24 17:01:06 +03:00
cn0363 scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
cn0501 projects/cn0501: Updated with axi_ad7768 IP for Coraz7s 2022-09-30 12:56:57 +03:00
cn0506 scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
cn0540 The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023) 2022-09-29 15:14:57 +03:00
cn0561 The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023) 2022-09-29 15:14:57 +03:00
cn0577 cn0577/zed: Update xdc to diff_term true. Disable csn in system_top 2022-09-21 09:42:40 +03:00
common projects/common: Add system_top _project templates 2022-09-20 17:00:49 +03:00
dac_fmc_ebz projects: Fix some Makefiles 2022-08-25 09:35:55 +03:00
daq2 projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
daq3 projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
fmcadc2 projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
fmcadc5 projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
fmcjesdadc1 projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
fmcomms2 projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
fmcomms5 projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
fmcomms8 projects/fmcomms8: Expose jesd params, add support for TX_JESD_L=4 2022-10-03 10:27:15 +03:00
fmcomms11 projects: Add fmc connection files for eval boards 2022-09-20 14:11:08 +03:00
imageon scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
m2k scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
pluto scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
pluto_ng scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
pulsar_adc_pmdz The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023) 2022-09-29 15:14:57 +03:00
scripts projects/scripts: Add fmc constraints generator script 2022-09-20 14:11:08 +03:00
sidekiqz2 scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
usrpe31x scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
Makefile Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Readme.md start adding some doc to the ./projects directory 2021-11-10 14:01:06 +02:00
wiki_summary.sh start adding some doc to the ./projects directory 2021-11-10 14:01:06 +02:00

Readme.md

Analog Devices HDL Projects

If you are reading this, you are likely looking for instructions on how to build one or more of the numerous projects that are maintained on https://github.com/analogdevicesinc/hdl and supported at http://ez.analog.com/fpga.

Top level instructions for building projects can be found at https://wiki.analog.com/resources/fpga/docs/hdl

Each project should have it's own Readme.md file which includes on-line pointers:

  • link to the board on https://www.analog.com/ that is being used
  • link(s) to product pages for parts on the board that interface with this HDL, so you can easily find datasheets
  • link to wiki doc for the board using this HDL
  • link to wiki doc for drivers (Linux or No-OS) for the HDL core (if there are any registers in the core)
  • link to wiki doc for drivers (Linux or No-OS) for the parts found on the board

As always, if you have questions - please ask on ADI's support community http://ez.analog.com/fpga