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tb
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Testbenches: Unify and optimize HDL testbenches
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2021-05-07 19:53:14 +03:00 |
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ad_3w_spi.v
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ad_3w_spi: Add a 4-wire to 3-wire SPI converter
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2019-08-28 16:13:12 +03:00 |
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ad_addsub.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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ad_adl5904_rst.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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ad_axis_inf_rx.v
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ad_axis_inf_rx: Initialize output ports to avoid X propagation in simulation
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2021-08-06 11:55:24 +03:00 |
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ad_b2g.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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ad_bus_mux.v
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Add generic fir filters processes for RF projects
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2019-08-20 16:24:47 +03:00 |
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ad_csc.v
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ad_csc: Fix warning for axi_hdmi_tx
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2020-09-11 10:23:53 +03:00 |
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ad_csc_CrYCb2RGB.v
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ad_csc_CrYCb2RGB: localparam can not be used in port definition
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2019-10-16 15:18:29 +03:00 |
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ad_csc_RGB2CrYCb.v
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ad_csc_RGB2CrYCb: localparam can not be used in port definition
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2019-10-16 15:18:29 +03:00 |
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ad_datafmt.v
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ad_datafmt: Add support for 8 bit data width
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2019-03-20 15:51:28 +02:00 |
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ad_dds.v
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library/common/ad_dds: Fix indentation
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2020-08-27 13:37:53 +03:00 |
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ad_dds_1.v
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ad_dds: Add selectable phase width option.
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2018-07-18 18:19:30 +03:00 |
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ad_dds_2.v
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ad_dds_2: Don't try to round if signal is not truncated
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2018-08-28 10:08:22 +02:00 |
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ad_dds_cordic_pipe.v
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ad_dds: Separated phase width from data width
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2018-07-18 18:19:30 +03:00 |
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ad_dds_sine.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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ad_dds_sine_cordic.v
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ad_dds: Fix synthesis updates
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2018-07-18 18:19:30 +03:00 |
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ad_edge_detect.v
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ad_edge_detect: Change port names
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2020-10-28 11:31:50 +02:00 |
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ad_g2b.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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ad_iobuf.v
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library: Move ad_iobuf to the common library, as it's not Xilinx specific
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2020-11-02 16:13:35 +02:00 |
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ad_iqcor.v
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common/ad_iqcor: Fix for sample width smaller than 16
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2020-04-24 16:38:54 +03:00 |
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ad_mem.v
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util_axis_fifo: instantiate block ram in async mode
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2018-04-11 15:09:54 +03:00 |
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ad_mem_asym.v
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ad_mem_asym: Force the Xilinx synthesizer to infer Block RAMs
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2020-01-13 12:25:23 +02:00 |
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ad_mux.v
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ad_mux: another fix cases where channel number is not power of mux size
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2020-11-27 09:45:11 +02:00 |
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ad_mux_core.v
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common/ad_mux: Pipelined mux, rtl and TB
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2020-11-27 09:45:11 +02:00 |
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ad_pack.v
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common/ad_pack: Generic packer core and testbench
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2021-02-05 15:24:15 +02:00 |
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ad_perfect_shuffle.v
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library: Add perfect shuffle module
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2018-10-15 15:34:31 +03:00 |
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ad_pngen.v
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ad_pngen: Generic PN generator
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2020-08-24 17:49:12 +03:00 |
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ad_pnmon.v
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ad_pnmon: Fix zero checking when valid not constant
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2021-01-26 15:22:41 +02:00 |
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ad_pps_receiver.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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ad_pps_receiver_constr.ttcl
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whitespace: Delete all trailing white spaces
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2019-06-07 10:20:15 +03:00 |
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ad_rst.v
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ad_rst: Synthesis attribute 'preserve' is redundant
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2018-08-14 17:54:14 +03:00 |
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ad_ss_422to444.v
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common/ad_ss_422to444.v: Fix warning
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2020-09-11 10:23:53 +03:00 |
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ad_ss_444to422.v
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ad_ss_444to422: localparam can not be used in port definition
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2019-10-16 15:18:29 +03:00 |
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ad_sysref_gen.v
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ad_sysref_gen: Fix quartus warnings
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2018-04-13 11:32:57 +02:00 |
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ad_tdd_control.v
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ad_tdd_control: Avoid single pulses if tx_only or rx_only
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2021-01-20 13:00:01 +02:00 |
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ad_upack.v
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common/ad_upack: Generic unpacker core and testbench
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2021-02-05 15:24:15 +02:00 |
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ad_xcvr_rx_if.v
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common/ad_xcvr_rx_if: make core more generic
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2018-12-04 14:02:22 +02:00 |
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axi_ctrlif.vhd
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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axi_streaming_dma_rx_fifo.vhd
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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axi_streaming_dma_tx_fifo.vhd
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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dma_fifo.vhd
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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pl330_dma_fifo.vhd
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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up_adc_channel.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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up_adc_common.v
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up_adc_common: Expose up version of r1_mode
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2020-08-24 17:49:12 +03:00 |
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up_axi.v
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up_axi.v: fixed bus width definition
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2019-08-06 13:45:54 +03:00 |
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up_clkgen.v
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dev info parameter update: Increase pcore version
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2019-03-30 11:26:11 +02:00 |
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up_clock_mon.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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up_dac_channel.v
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up_dac_channel: add register for dma data xbar
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2020-11-27 09:45:11 +02:00 |
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up_dac_common.v
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common/up_dac_common: Expose r1_mode in up clock domain to prevent deadlock
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2021-05-26 15:44:45 +03:00 |
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up_delay_cntrl.v
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up_delay_cntrl:ad_serdes_in: Make delay value width parametrizable
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2020-08-07 08:31:19 +03:00 |
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up_hdmi_rx.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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up_hdmi_tx.v
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axi_hdmi_tx: Update register initialization
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2020-09-25 12:56:53 +03:00 |
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up_pmod.v
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ad_rst: Update all the modules, which instantiate the ad_rst
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2018-08-06 21:24:41 +03:00 |
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up_tdd_cntrl.v
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up_tdd_cntrl: Add magic value "TDDC"
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2021-06-14 16:50:59 +03:00 |
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up_xfer_cntrl.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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up_xfer_status.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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util_axis_upscale.v
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util_axis_upscale: Sign extension must be done separately for each channel
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2019-06-28 11:18:29 +03:00 |
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util_dec256sinc24b.v
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util_dec256sinc24b: Fix the accumulator
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2019-06-28 11:18:29 +03:00 |
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util_delay.v
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license: Fix a spelling mistake
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2018-04-11 15:09:54 +03:00 |
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util_pulse_gen.v
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util_pulse_gen: Expose the internal counter
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2019-08-08 14:26:07 +03:00 |
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