109 lines
3.9 KiB
Verilog
109 lines
3.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// data format (offset binary or 2's complement only)
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`timescale 1ps/1ps
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module ad_datafmt (
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// data path
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clk,
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valid,
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data,
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valid_out,
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data_out,
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// control signals
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dfmt_enable,
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dfmt_type,
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dfmt_se);
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// delayed data bus width
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parameter DATA_WIDTH = 16;
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localparam DW = DATA_WIDTH - 1;
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// data path
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input clk;
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input valid;
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input [DW:0] data;
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output valid_out;
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output [15:0] data_out;
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// control signals
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input dfmt_enable;
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input dfmt_type;
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input dfmt_se;
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// internal registers
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reg valid_out = 'd0;
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reg [15:0] data_out = 'd0;
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// internal signals
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wire type_s;
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wire signext_s;
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wire [DW:0] data_s;
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wire [23:0] sign_s;
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wire [23:0] data_out_s;
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// if offset-binary convert to 2's complement first
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assign type_s = dfmt_enable & dfmt_type;
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assign signext_s = dfmt_enable & dfmt_se;
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assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data;
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assign sign_s = (signext_s == 1'b1) ? {{24{data_s[DW]}}} : 24'd0;
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assign data_out_s = {sign_s[23:(DW+1)], data_s};
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always @(posedge clk) begin
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valid_out <= valid;
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data_out <= data_out_s[15:0];
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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