192 lines
6.2 KiB
Verilog
192 lines
6.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_clkgen #(
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parameter ID = 0,
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parameter [ 7:0] FPGA_TECHNOLOGY = 0,
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parameter [ 7:0] FPGA_FAMILY = 0,
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parameter [ 7:0] SPEED_GRADE = 0,
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parameter [ 7:0] DEV_PACKAGE = 0,
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parameter [15:0] FPGA_VOLTAGE = 0) (
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// mmcm reset
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output mmcm_rst,
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// clock selection
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output clk_sel,
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// drp interface
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output reg up_drp_sel,
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output reg up_drp_wr,
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output reg [11:0] up_drp_addr,
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output reg [15:0] up_drp_wdata,
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input [15:0] up_drp_rdata,
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input up_drp_ready,
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input up_drp_locked,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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localparam PCORE_VERSION = 32'h00050063;
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// internal registers
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reg up_mmcm_preset = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_mmcm_resetn = 'd0;
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reg up_resetn = 'd0;
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reg up_drp_status = 'd0;
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reg up_drp_rwn = 'd0;
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reg [15:0] up_drp_rdata_hold = 'd0;
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reg up_clk_sel = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
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assign clk_sel = ~up_clk_sel;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_mmcm_preset <= 1'd1;
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_mmcm_resetn <= 'd0;
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up_resetn <= 'd0;
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up_drp_sel <= 'd0;
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up_drp_wr <= 'd0;
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up_drp_status <= 'd0;
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up_drp_rwn <= 'd0;
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up_drp_addr <= 'd0;
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up_drp_wdata <= 'd0;
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up_drp_rdata_hold <= 'd0;
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up_clk_sel <= 'd0;
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end else begin
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up_mmcm_preset <= ~up_mmcm_resetn;
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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up_mmcm_resetn <= up_wdata[1];
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up_resetn <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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up_clk_sel <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
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up_drp_sel <= 1'b1;
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up_drp_wr <= ~up_wdata[28];
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end else begin
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up_drp_sel <= 1'b0;
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up_drp_wr <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
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up_drp_status <= 1'b1;
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end else if (up_drp_ready == 1'b1) begin
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up_drp_status <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
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up_drp_rwn <= up_wdata[28];
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up_drp_addr <= up_wdata[27:16];
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up_drp_wdata <= up_wdata[15:0];
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end
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if (up_drp_ready == 1'b1) begin
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up_drp_rdata_hold <= up_drp_rdata;
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00: up_rdata <= PCORE_VERSION;
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8'h01: up_rdata <= ID;
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8'h02: up_rdata <= up_scratch;
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8'h07: up_rdata <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
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8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
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8'h11: up_rdata <= {31'd0, up_clk_sel};
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8'h17: up_rdata <= {31'd0, up_drp_locked};
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8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
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8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
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8'h50: up_rdata <= {16'd0, FPGA_VOLTAGE}; // mV
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// resets
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ad_rst i_mmcm_rst_reg (.rst_async(up_mmcm_preset), .clk(up_clk), .rstn(), .rst(mmcm_rst));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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