Istvan Csomortani 10d9de39a1 axi_ad9361/tdd: Update the synchronization logic ... The master will regenerate a sync pulse periodically. The period can be defined by software.		2015-08-19 12:21:23 +03:00
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Makefile	axi_ad9361: Update Make file	2015-08-19 12:14:03 +03:00
axi_ad9361.v	axi_ad9361/tdd: Update the synchronization logic	2015-08-19 12:21:23 +03:00
axi_ad9361_alt_lvds_rx.v	Add .gitattributes file	2015-07-01 18:43:51 +02:00
axi_ad9361_alt_lvds_tx.v	Add .gitattributes file	2015-07-01 18:43:51 +02:00
axi_ad9361_constr.xdc	axi_ad9361: Add ASYNC_REG properties to CDC regs and add missing -datapath_only	2015-04-21 10:15:02 +02:00
axi_ad9361_dev_if.v	Add .gitattributes file	2015-07-01 18:43:51 +02:00
axi_ad9361_dev_if_alt.v	axi_ad9361: Updated altera core by including tdd related files. Removed deleted ports	2015-07-24 16:41:41 +03:00
axi_ad9361_hw.tcl	Merge branch 'master' into dev	2015-08-17 15:15:58 +03:00
axi_ad9361_ip.tcl	fmcomms2/TDD: Update synchronization interface	2015-08-06 15:14:36 +03:00
axi_ad9361_rx.v	Add .gitattributes file	2015-07-01 18:43:51 +02:00
axi_ad9361_rx_channel.v	ad_iqcor- changes	2015-07-23 16:20:46 -04:00
axi_ad9361_rx_pnmon.v	Add .gitattributes file	2015-07-01 18:43:51 +02:00
axi_ad9361_tdd.v	axi_ad9361/tdd: Update the synchronization logic	2015-08-19 12:21:23 +03:00
axi_ad9361_tdd_if.v	axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch	2015-06-04 18:09:47 +03:00
axi_ad9361_tx.v	Add .gitattributes file	2015-07-01 18:43:51 +02:00
axi_ad9361_tx_channel.v	ad_iqcor- changes	2015-07-23 16:20:46 -04:00