203 lines
6.6 KiB
Verilog
203 lines
6.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_delay_cntrl (
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// delay interface
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delay_clk,
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delay_rst,
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delay_locked,
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// io interface
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up_dld,
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up_dwdata,
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up_drdata,
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// processor interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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parameter IO_WIDTH = 8;
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parameter IO_BASEADDR = 6'h02;
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// delay interface
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input delay_clk;
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output delay_rst;
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input delay_locked;
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// io interface
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output [(IO_WIDTH-1):0] up_dld;
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output [((IO_WIDTH*5)-1):0] up_dwdata;
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input [((IO_WIDTH*5)-1):0] up_drdata;
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// processor interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal registers
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reg up_preset = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_dlocked_m1 = 'd0;
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reg up_dlocked = 'd0;
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reg [(IO_WIDTH-1):0] up_dld = 'd0;
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reg [((IO_WIDTH*5)-1):0] up_dwdata = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire [ 4:0] up_rdata_s;
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wire [(IO_WIDTH-1):0] up_drdata4_s;
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wire [(IO_WIDTH-1):0] up_drdata3_s;
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wire [(IO_WIDTH-1):0] up_drdata2_s;
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wire [(IO_WIDTH-1):0] up_drdata1_s;
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wire [(IO_WIDTH-1):0] up_drdata0_s;
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// variables
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genvar n;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == IO_BASEADDR) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == IO_BASEADDR) ? up_rreq : 1'b0;
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assign up_rdata_s[4] = | up_drdata4_s;
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assign up_rdata_s[3] = | up_drdata3_s;
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assign up_rdata_s[2] = | up_drdata2_s;
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assign up_rdata_s[1] = | up_drdata1_s;
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assign up_rdata_s[0] = | up_drdata0_s;
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generate
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for (n = 0; n < IO_WIDTH; n = n + 1) begin: g_drd
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assign up_drdata4_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+4)] : 1'd0;
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assign up_drdata3_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+3)] : 1'd0;
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assign up_drdata2_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+2)] : 1'd0;
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assign up_drdata1_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+1)] : 1'd0;
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assign up_drdata0_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+0)] : 1'd0;
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end
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endgenerate
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// processor interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_preset <= 1'd1;
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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up_dlocked_m1 <= 'd0;
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up_dlocked <= 'd0;
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end else begin
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up_preset <= 1'd0;
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up_wack <= up_wreq_s;
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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if (up_dlocked == 1'b0) begin
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up_rdata <= 32'hffffffff;
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end else begin
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up_rdata <= {27'd0, up_rdata_s};
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end
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end else begin
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up_rdata <= 32'd0;
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end
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up_dlocked_m1 <= delay_locked;
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up_dlocked <= up_dlocked_m1;
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end
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end
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// write does not hold- read back what goes into effect.
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generate
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for (n = 0; n < IO_WIDTH; n = n + 1) begin: g_dwr
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_dld[n] <= 'd0;
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up_dwdata[((n*5)+4):(n*5)] <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == n)) begin
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up_dld[n] <= 1'd1;
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up_dwdata[((n*5)+4):(n*5)] <= up_wdata[4:0];
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end else begin
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up_dld[n] <= 1'd0;
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up_dwdata[((n*5)+4):(n*5)] <= up_dwdata[((n*5)+4):(n*5)];
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end
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end
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end
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end
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endgenerate
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// resets
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ad_rst i_delay_rst_reg (
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.preset (up_preset),
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.clk (delay_clk),
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.rst (delay_rst));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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