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Deleted lines after endmodule and consecutive empty lines. Modified parentheses, extra spaces. Fixed indentation. Fixed parameters list to be each parameter on its line. Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com> |
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Readme.md |
Readme.md
AD9467-FMC HDL Project
Here are some pointers to help you:
- Board Product Page
- Parts : 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter
- Project Doc: https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467
- HDL Doc: https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467
- Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl