157afcbc33
The tb_base.v verilog files does not contain a full module definition, just some plain test code. In general the files is sourced inside the test bench main module. As is, defining a timescale in these files will generate an error, because timescale directive can not be inside a module. Delete all the timescale directive from these files. |
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| .. | ||
| axi_read_slave.v | ||
| axi_slave.v | ||
| axi_write_slave.v | ||
| dma_read_shutdown_tb | ||
| dma_read_shutdown_tb.v | ||
| dma_read_tb | ||
| dma_read_tb.v | ||
| dma_write_shutdown_tb | ||
| dma_write_shutdown_tb.v | ||
| dma_write_tb | ||
| dma_write_tb.v | ||
| regmap_tb | ||
| regmap_tb.v | ||
| reset_manager_tb | ||
| reset_manager_tb.v | ||
| run_tb.sh | ||
| tb_base.v | ||