693 lines
20 KiB
Verilog
693 lines
20 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
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ddr3_reset_n,
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ddr3_we_n,
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iic_scl,
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iic_sda,
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rx_ref_clk_p,
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rx_ref_clk_n,
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rx_sysref_p,
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rx_sysref_n,
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rx_sync_p,
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rx_sync_n,
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rx_data_p,
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rx_data_n,
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tx_ref_clk_p,
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tx_ref_clk_n,
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tx_sysref_p,
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tx_sysref_n,
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tx_sync0_p,
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tx_sync0_n,
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tx_sync1_p,
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tx_sync1_n,
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tx_data_p,
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tx_data_n,
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trig_p,
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trig_n,
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spi_csn_clk,
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spi_csn_dac,
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spi_csn_adc,
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spi_clk,
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spi_sdio,
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spi_dir,
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spi2_csn_adf4355_1,
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spi2_csn_adf4355_2,
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spi2_csn_hmc1044_1,
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spi2_csn_hmc1044_2,
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spi2_csn_hmc1044_3,
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spi2_csn_adl5240_1,
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spi2_csn_adl5240_2,
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spi2_csn_hmc271_1,
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spi2_csn_hmc271_2,
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spi2_clk,
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spi2_sdo,
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spi2_sdi_hmc271_1,
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spi2_sdi_hmc271_2,
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clk_gpio,
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adc_fda,
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adc_fdb,
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dac_irq,
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adf4355_1_ld,
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adf4355_2_ld,
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xo_en,
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clk_sync,
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adf4355_2_pd,
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dac_txen0,
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dac_txen1,
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hmc271_1_reset,
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hmc271_2_reset,
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hmc349_sel,
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hmc922_a,
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hmc922_b);
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inout [ 14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [ 31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [ 53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout [ 14:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [ 23:0] hdmi_data;
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output spdif;
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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output [ 13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [ 63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output ddr3_ras_n;
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output ddr3_reset_n;
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output ddr3_we_n;
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inout iic_scl;
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inout iic_sda;
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input rx_ref_clk_p;
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input rx_ref_clk_n;
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input rx_sysref_p;
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input rx_sysref_n;
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output rx_sync_p;
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output rx_sync_n;
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input [ 3:0] rx_data_p;
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input [ 3:0] rx_data_n;
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input tx_ref_clk_p;
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input tx_ref_clk_n;
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input tx_sysref_p;
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input tx_sysref_n;
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input tx_sync0_p;
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input tx_sync0_n;
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input tx_sync1_p;
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input tx_sync1_n;
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output [ 7:0] tx_data_p;
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output [ 7:0] tx_data_n;
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input trig_p;
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input trig_n;
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output spi_csn_clk;
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output spi_csn_dac;
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output spi_csn_adc;
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output spi_clk;
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inout spi_sdio;
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output spi_dir;
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output spi2_csn_adf4355_1;
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output spi2_csn_adf4355_2;
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output spi2_csn_hmc1044_1;
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output spi2_csn_hmc1044_2;
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output spi2_csn_hmc1044_3;
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output spi2_csn_adl5240_1;
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output spi2_csn_adl5240_2;
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output spi2_csn_hmc271_1;
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output spi2_csn_hmc271_2;
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output spi2_clk;
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output spi2_sdo;
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input spi2_sdi_hmc271_1;
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input spi2_sdi_hmc271_2;
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inout [ 3:0] clk_gpio;
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inout adc_fda;
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inout adc_fdb;
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inout dac_irq;
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inout adf4355_1_ld;
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inout adf4355_2_ld;
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inout xo_en;
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inout clk_sync;
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inout adf4355_2_pd;
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inout dac_txen0;
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inout dac_txen1;
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inout hmc271_1_reset;
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inout hmc271_2_reset;
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inout hmc349_sel;
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inout hmc922_a;
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inout hmc922_b;
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// internal registers
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reg dac_drd = 'd0;
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reg [ 63:0] dac_ddata_0 = 'd0;
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reg [ 63:0] dac_ddata_1 = 'd0;
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reg [ 63:0] dac_ddata_2 = 'd0;
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reg [ 63:0] dac_ddata_3 = 'd0;
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reg adc_dsync = 'd0;
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reg adc_dwr = 'd0;
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reg [127:0] adc_ddata = 'd0;
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// internal signals
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire [ 63:0] gpio_t;
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wire [ 2:0] spi0_csn;
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wire spi0_clk;
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wire spi0_mosi;
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wire spi0_miso;
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wire [ 2:0] spi1_csn;
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wire spi1_clk;
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wire spi1_mosi;
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wire spi1_miso;
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wire [ 11:0] spi2_csn;
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wire spi2_mosi;
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wire spi2_miso;
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wire trig;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire tx_ref_clk;
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wire tx_sysref;
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wire tx_sync0;
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wire tx_sync1;
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wire tx_sync;
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wire dac_clk;
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wire [255:0] dac_ddata;
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wire dac_enable_0;
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wire dac_enable_1;
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wire dac_enable_2;
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wire dac_enable_3;
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wire dac_valid_0;
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wire dac_valid_1;
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wire dac_valid_2;
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wire dac_valid_3;
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wire adc_clk;
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wire [ 63:0] adc_data_0;
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wire [ 63:0] adc_data_1;
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wire adc_enable_0;
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wire adc_enable_1;
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wire adc_valid_0;
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wire adc_valid_1;
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// adc-dac data
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always @(posedge dac_clk) begin
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case ({dac_enable_3, dac_enable_2, dac_enable_1, dac_enable_0})
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4'b1111: begin
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dac_drd <= dac_valid_0 & dac_valid_1 & dac_valid_2 & dac_valid_3;
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dac_ddata_0[15: 0] <= dac_ddata[((16* 0)+15):(16* 0)];
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dac_ddata_1[15: 0] <= dac_ddata[((16* 1)+15):(16* 1)];
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dac_ddata_2[15: 0] <= dac_ddata[((16* 2)+15):(16* 2)];
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dac_ddata_3[15: 0] <= dac_ddata[((16* 3)+15):(16* 3)];
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dac_ddata_0[31:16] <= dac_ddata[((16* 4)+15):(16* 4)];
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dac_ddata_1[31:16] <= dac_ddata[((16* 5)+15):(16* 5)];
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dac_ddata_2[31:16] <= dac_ddata[((16* 6)+15):(16* 6)];
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dac_ddata_3[31:16] <= dac_ddata[((16* 7)+15):(16* 7)];
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dac_ddata_0[47:32] <= dac_ddata[((16* 8)+15):(16* 8)];
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dac_ddata_1[47:32] <= dac_ddata[((16* 9)+15):(16* 9)];
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dac_ddata_2[47:32] <= dac_ddata[((16*10)+15):(16*10)];
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dac_ddata_3[47:32] <= dac_ddata[((16*11)+15):(16*11)];
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dac_ddata_0[63:48] <= dac_ddata[((16*12)+15):(16*12)];
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dac_ddata_1[63:48] <= dac_ddata[((16*13)+15):(16*13)];
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dac_ddata_2[63:48] <= dac_ddata[((16*14)+15):(16*14)];
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dac_ddata_3[63:48] <= dac_ddata[((16*15)+15):(16*15)];
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end
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4'b1100: begin
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dac_drd <= dac_valid_2 & dac_valid_3 & ~dac_drd;
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dac_ddata_0 <= 64'd0;
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dac_ddata_1 <= 64'd0;
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if (dac_drd == 1'b1) begin
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dac_ddata_2[15: 0] <= dac_ddata[((16* 0)+15):(16* 0)];
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dac_ddata_3[15: 0] <= dac_ddata[((16* 1)+15):(16* 1)];
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dac_ddata_2[31:16] <= dac_ddata[((16* 2)+15):(16* 2)];
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dac_ddata_3[31:16] <= dac_ddata[((16* 3)+15):(16* 3)];
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dac_ddata_2[47:32] <= dac_ddata[((16* 4)+15):(16* 4)];
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dac_ddata_3[47:32] <= dac_ddata[((16* 5)+15):(16* 5)];
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dac_ddata_2[63:48] <= dac_ddata[((16* 6)+15):(16* 6)];
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dac_ddata_3[63:48] <= dac_ddata[((16* 7)+15):(16* 7)];
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end else begin
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dac_ddata_2[15: 0] <= dac_ddata[((16* 8)+15):(16* 8)];
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dac_ddata_3[15: 0] <= dac_ddata[((16* 9)+15):(16* 9)];
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dac_ddata_2[31:16] <= dac_ddata[((16*10)+15):(16*10)];
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dac_ddata_3[31:16] <= dac_ddata[((16*11)+15):(16*11)];
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dac_ddata_2[47:32] <= dac_ddata[((16*12)+15):(16*12)];
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dac_ddata_3[47:32] <= dac_ddata[((16*13)+15):(16*13)];
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dac_ddata_2[63:48] <= dac_ddata[((16*14)+15):(16*14)];
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dac_ddata_3[63:48] <= dac_ddata[((16*15)+15):(16*15)];
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end
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end
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4'b0011: begin
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dac_drd <= dac_valid_0 & dac_valid_1 & ~dac_drd;
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dac_ddata_2 <= 64'd0;
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dac_ddata_3 <= 64'd0;
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if (dac_drd == 1'b1) begin
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dac_ddata_0[15: 0] <= dac_ddata[((16* 0)+15):(16* 0)];
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dac_ddata_1[15: 0] <= dac_ddata[((16* 1)+15):(16* 1)];
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dac_ddata_0[31:16] <= dac_ddata[((16* 2)+15):(16* 2)];
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dac_ddata_1[31:16] <= dac_ddata[((16* 3)+15):(16* 3)];
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dac_ddata_0[47:32] <= dac_ddata[((16* 4)+15):(16* 4)];
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dac_ddata_1[47:32] <= dac_ddata[((16* 5)+15):(16* 5)];
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dac_ddata_0[63:48] <= dac_ddata[((16* 6)+15):(16* 6)];
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dac_ddata_1[63:48] <= dac_ddata[((16* 7)+15):(16* 7)];
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end else begin
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dac_ddata_0[15: 0] <= dac_ddata[((16* 8)+15):(16* 8)];
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dac_ddata_1[15: 0] <= dac_ddata[((16* 9)+15):(16* 9)];
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dac_ddata_0[31:16] <= dac_ddata[((16*10)+15):(16*10)];
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dac_ddata_1[31:16] <= dac_ddata[((16*11)+15):(16*11)];
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dac_ddata_0[47:32] <= dac_ddata[((16*12)+15):(16*12)];
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dac_ddata_1[47:32] <= dac_ddata[((16*13)+15):(16*13)];
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dac_ddata_0[63:48] <= dac_ddata[((16*14)+15):(16*14)];
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dac_ddata_1[63:48] <= dac_ddata[((16*15)+15):(16*15)];
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end
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end
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default: begin
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dac_drd <= 1'b0;
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dac_ddata_0 <= 64'd0;
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dac_ddata_1 <= 64'd0;
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dac_ddata_2 <= 64'd0;
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dac_ddata_3 <= 64'd0;
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end
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endcase
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end
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always @(posedge adc_clk) begin
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case ({adc_enable_1, adc_enable_0})
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2'b11: begin
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adc_dsync <= 1'b1;
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adc_dwr <= adc_valid_1 & adc_valid_0;
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adc_ddata[127:112] <= adc_data_1[63:48];
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adc_ddata[111: 96] <= adc_data_0[63:48];
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adc_ddata[ 95: 80] <= adc_data_1[47:32];
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adc_ddata[ 79: 64] <= adc_data_0[47:32];
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adc_ddata[ 63: 48] <= adc_data_1[31:16];
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adc_ddata[ 47: 32] <= adc_data_0[31:16];
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adc_ddata[ 31: 16] <= adc_data_1[15: 0];
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adc_ddata[ 15: 0] <= adc_data_0[15: 0];
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end
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2'b10: begin
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adc_dsync <= 1'b1;
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adc_dwr <= adc_valid_1 & ~adc_dwr;
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adc_ddata[127:112] <= adc_data_1[63:48];
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adc_ddata[111: 96] <= adc_data_1[47:32];
|
|
adc_ddata[ 95: 80] <= adc_data_1[31:16];
|
|
adc_ddata[ 79: 64] <= adc_data_1[15: 0];
|
|
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
|
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
|
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
|
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
|
end
|
|
2'b01: begin
|
|
adc_dsync <= 1'b1;
|
|
adc_dwr <= adc_valid_0 & ~adc_dwr;
|
|
adc_ddata[127:112] <= adc_data_0[63:48];
|
|
adc_ddata[111: 96] <= adc_data_0[47:32];
|
|
adc_ddata[ 95: 80] <= adc_data_0[31:16];
|
|
adc_ddata[ 79: 64] <= adc_data_0[15: 0];
|
|
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
|
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
|
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
|
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
|
end
|
|
default: begin
|
|
adc_dsync <= 1'b0;
|
|
adc_dwr <= 1'b0;
|
|
adc_ddata <= 128'd0;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// spi
|
|
|
|
assign spi_csn_adc = spi0_csn[2];
|
|
assign spi_csn_dac = spi0_csn[1];
|
|
assign spi_csn_clk = spi0_csn[0];
|
|
|
|
// instantiations
|
|
|
|
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
|
|
.CEB (1'd0),
|
|
.I (rx_ref_clk_p),
|
|
.IB (rx_ref_clk_n),
|
|
.O (rx_ref_clk),
|
|
.ODIV2 ());
|
|
|
|
IBUFDS i_ibufds_rx_sysref (
|
|
.I (rx_sysref_p),
|
|
.IB (rx_sysref_n),
|
|
.O (rx_sysref));
|
|
|
|
OBUFDS i_obufds_rx_sync (
|
|
.I (rx_sync),
|
|
.O (rx_sync_p),
|
|
.OB (rx_sync_n));
|
|
|
|
IBUFDS_GTE2 i_ibufds_tx_ref_clk (
|
|
.CEB (1'd0),
|
|
.I (tx_ref_clk_p),
|
|
.IB (tx_ref_clk_n),
|
|
.O (tx_ref_clk),
|
|
.ODIV2 ());
|
|
|
|
IBUFDS i_ibufds_tx_sysref (
|
|
.I (tx_sysref_p),
|
|
.IB (tx_sysref_n),
|
|
.O (tx_sysref));
|
|
|
|
IBUFDS i_ibufds_tx_sync0 (
|
|
.I (tx_sync0_p),
|
|
.IB (tx_sync0_n),
|
|
.O (tx_sync0));
|
|
|
|
IBUFDS i_ibufds_tx_sync1 (
|
|
.I (tx_sync1_p),
|
|
.IB (tx_sync1_n),
|
|
.O (tx_sync1));
|
|
|
|
assign tx_sync = tx_sync0 & tx_sync1;
|
|
|
|
fmcomms7_spi i_spi (
|
|
.spi_csn (spi0_csn),
|
|
.spi_clk (spi_clk),
|
|
.spi_mosi (spi0_mosi),
|
|
.spi_miso (spi0_miso),
|
|
.spi_sdio (spi_sdio),
|
|
.spi_dir (spi_dir));
|
|
|
|
IBUFDS i_ibufds_trig (
|
|
.I (trig_p),
|
|
.IB (trig_n),
|
|
.O (trig));
|
|
|
|
assign spi2_csn_adf4355_1 = spi2_csn[0];
|
|
assign spi2_csn_adf4355_2 = spi2_csn[1];
|
|
assign spi2_csn_hmc1044_1 = spi2_csn[2];
|
|
assign spi2_csn_hmc1044_2 = spi2_csn[3];
|
|
assign spi2_csn_hmc1044_3 = spi2_csn[4];
|
|
assign spi2_csn_adl5240_1 = spi2_csn[5];
|
|
assign spi2_csn_adl5240_2 = spi2_csn[6];
|
|
assign spi2_csn_hmc271_1 = spi2_csn[7];
|
|
assign spi2_csn_hmc271_2 = spi2_csn[8];
|
|
assign spi2_sdo = spi2_mosi;
|
|
assign spi2_miso = (~spi2_csn[7] & spi2_sdi_hmc271_1) |
|
|
(~spi2_csn[8] & spi2_sdi_hmc271_2);
|
|
|
|
assign gpio_i[51] = trig;
|
|
assign spi_clk = spi0_clk;
|
|
|
|
ad_iobuf #(.DATA_WIDTH(19)) i_iobuf (
|
|
.dt (gpio_t[50:32]),
|
|
.di (gpio_o[50:32]),
|
|
.do (gpio_i[50:32]),
|
|
.dio ({ xo_en, // 50
|
|
clk_sync, // 49
|
|
adf4355_2_pd, // 48
|
|
dac_txen0, // 47
|
|
dac_txen1, // 46
|
|
hmc271_1_reset, // 45
|
|
hmc271_2_reset, // 44
|
|
hmc349_sel, // 43
|
|
hmc922_a, // 42
|
|
hmc922_b, // 41
|
|
adf4355_2_ld, // 40
|
|
adf4355_1_ld, // 39
|
|
dac_irq, // 38
|
|
adc_fdb, // 37
|
|
adc_fda, // 36
|
|
clk_gpio[3], // 35
|
|
clk_gpio[2], // 34
|
|
clk_gpio[1], // 33
|
|
clk_gpio[0]})); // 32
|
|
|
|
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
|
|
.dt (gpio_t[14:0]),
|
|
.di (gpio_o[14:0]),
|
|
.do (gpio_i[14:0]),
|
|
.dio (gpio_bd));
|
|
|
|
system_wrapper i_system_wrapper (
|
|
.adc_clk (adc_clk),
|
|
.adc_data_0 (adc_data_0),
|
|
.adc_data_1 (adc_data_1),
|
|
.adc_ddata (adc_ddata),
|
|
.adc_dsync (adc_dsync),
|
|
.adc_dwr (adc_dwr),
|
|
.adc_enable_0 (adc_enable_0),
|
|
.adc_enable_1 (adc_enable_1),
|
|
.adc_valid_0 (adc_valid_0),
|
|
.adc_valid_1 (adc_valid_1),
|
|
.dac_clk (dac_clk),
|
|
.dac_ddata (dac_ddata),
|
|
.dac_ddata_0 (dac_ddata_0),
|
|
.dac_ddata_1 (dac_ddata_1),
|
|
.dac_ddata_2 (dac_ddata_2),
|
|
.dac_ddata_3 (dac_ddata_3),
|
|
.dac_drd (dac_drd),
|
|
.dac_enable_0 (dac_enable_0),
|
|
.dac_enable_1 (dac_enable_1),
|
|
.dac_enable_2 (dac_enable_2),
|
|
.dac_enable_3 (dac_enable_3),
|
|
.dac_valid_0 (dac_valid_0),
|
|
.dac_valid_1 (dac_valid_1),
|
|
.dac_valid_2 (dac_valid_2),
|
|
.dac_valid_3 (dac_valid_3),
|
|
.ddr3_addr (ddr3_addr),
|
|
.ddr3_ba (ddr3_ba),
|
|
.ddr3_cas_n (ddr3_cas_n),
|
|
.ddr3_ck_n (ddr3_ck_n),
|
|
.ddr3_ck_p (ddr3_ck_p),
|
|
.ddr3_cke (ddr3_cke),
|
|
.ddr3_cs_n (ddr3_cs_n),
|
|
.ddr3_dm (ddr3_dm),
|
|
.ddr3_dq (ddr3_dq),
|
|
.ddr3_dqs_n (ddr3_dqs_n),
|
|
.ddr3_dqs_p (ddr3_dqs_p),
|
|
.ddr3_odt (ddr3_odt),
|
|
.ddr3_ras_n (ddr3_ras_n),
|
|
.ddr3_reset_n (ddr3_reset_n),
|
|
.ddr3_we_n (ddr3_we_n),
|
|
.ddr_addr (ddr_addr),
|
|
.ddr_ba (ddr_ba),
|
|
.ddr_cas_n (ddr_cas_n),
|
|
.ddr_ck_n (ddr_ck_n),
|
|
.ddr_ck_p (ddr_ck_p),
|
|
.ddr_cke (ddr_cke),
|
|
.ddr_cs_n (ddr_cs_n),
|
|
.ddr_dm (ddr_dm),
|
|
.ddr_dq (ddr_dq),
|
|
.ddr_dqs_n (ddr_dqs_n),
|
|
.ddr_dqs_p (ddr_dqs_p),
|
|
.ddr_odt (ddr_odt),
|
|
.ddr_ras_n (ddr_ras_n),
|
|
.ddr_reset_n (ddr_reset_n),
|
|
.ddr_we_n (ddr_we_n),
|
|
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
|
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
|
.fixed_io_mio (fixed_io_mio),
|
|
.fixed_io_ps_clk (fixed_io_ps_clk),
|
|
.fixed_io_ps_porb (fixed_io_ps_porb),
|
|
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
|
.gpio_i (gpio_i),
|
|
.gpio_o (gpio_o),
|
|
.gpio_t (gpio_t),
|
|
.hdmi_data (hdmi_data),
|
|
.hdmi_data_e (hdmi_data_e),
|
|
.hdmi_hsync (hdmi_hsync),
|
|
.hdmi_out_clk (hdmi_out_clk),
|
|
.hdmi_vsync (hdmi_vsync),
|
|
.iic_main_scl_io (iic_scl),
|
|
.iic_main_sda_io (iic_sda),
|
|
.ps_intr_00 (1'b0),
|
|
.ps_intr_01 (1'b0),
|
|
.ps_intr_02 (1'b0),
|
|
.ps_intr_03 (1'b0),
|
|
.ps_intr_04 (1'b0),
|
|
.ps_intr_05 (1'b0),
|
|
.ps_intr_06 (1'b0),
|
|
.ps_intr_07 (1'b0),
|
|
.ps_intr_08 (1'b0),
|
|
.ps_intr_11 (1'b0),
|
|
.rx_data_n (rx_data_n),
|
|
.rx_data_p (rx_data_p),
|
|
.rx_ref_clk (rx_ref_clk),
|
|
.rx_sync (rx_sync),
|
|
.rx_sysref (rx_sysref),
|
|
.spdif (spdif),
|
|
.spi0_clk_i (spi0_clk),
|
|
.spi0_clk_o (spi0_clk),
|
|
.spi0_csn_0_o (spi0_csn[0]),
|
|
.spi0_csn_1_o (spi0_csn[1]),
|
|
.spi0_csn_2_o (spi0_csn[2]),
|
|
.spi0_csn_i (1'b1),
|
|
.spi0_sdi_i (spi0_miso),
|
|
.spi0_sdo_i (spi0_mosi),
|
|
.spi0_sdo_o (spi0_mosi),
|
|
.spi1_clk_i (spi1_clk),
|
|
.spi1_clk_o (spi1_clk),
|
|
.spi1_csn_0_o (spi1_csn[0]),
|
|
.spi1_csn_1_o (spi1_csn[1]),
|
|
.spi1_csn_2_o (spi1_csn[2]),
|
|
.spi1_csn_i (1'b1),
|
|
.spi1_sdi_i (1'b1),
|
|
.spi1_sdo_i (spi1_mosi),
|
|
.spi1_sdo_o (spi1_mosi),
|
|
.spi2_clk_i (spi2_clk),
|
|
.spi2_clk_o (spi2_clk),
|
|
.spi2_csn_i (12'hfff),
|
|
.spi2_csn_o (spi2_csn),
|
|
.spi2_sdi_i (spi2_miso),
|
|
.spi2_sdo_i (spi2_mosi),
|
|
.spi2_sdo_o (spi2_mosi),
|
|
.sys_clk_clk_n (sys_clk_n),
|
|
.sys_clk_clk_p (sys_clk_p),
|
|
.sys_rst (sys_rst),
|
|
.tx_data_n (tx_data_n),
|
|
.tx_data_p (tx_data_p),
|
|
.tx_ref_clk (tx_ref_clk),
|
|
.tx_sync (tx_sync),
|
|
.tx_sysref (tx_sysref));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|