Istvan Csomortani 572cd10c35 avl_dacfifo: Fix reset architecture in avl_dacfifo_rd ... Make sure that all address registers are reset during the initialization phase of the FIFO.		2017-11-03 09:29:43 +00:00
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adi_jesd204	jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps	2017-10-25 14:36:54 +01:00
avl_adxcfg	avl_adxcfg: Consistently use non-blocking assignments	2017-07-24 16:06:00 +02:00
avl_adxcvr	avl_adxcvr: Perform octet order swap	2017-08-03 17:57:58 +02:00
avl_adxcvr_octet_swap	avl_adxcvr: Perform octet order swap	2017-08-03 17:57:58 +02:00
avl_adxphy	avl_adxcvr: Simplify TX lane mapping	2017-08-03 17:57:58 +02:00
avl_dacfifo	avl_dacfifo: Fix reset architecture in avl_dacfifo_rd	2017-11-03 09:29:43 +00:00
axi_adxcvr	axi_adxcvr: Avoid implicit signal truncation warning	2017-08-07 17:42:17 +02:00
common	altera/ad_mem_asym: Delete it, QSYS flow is used	2017-09-25 08:57:26 +01:00
jesd204_phy	jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps	2017-10-25 14:36:54 +01:00