72 lines
2.4 KiB
Tcl
72 lines
2.4 KiB
Tcl
###############################################################################
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## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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package require qsys 14.0
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source ../../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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ad_ip_create util_adcfifo {UTIL ADC FIFO IP core}
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set_module_property ELABORATION_CALLBACK p_util_adcfifo
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# files
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ad_ip_files util_adcfifo [list\
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$ad_hdl_dir/library/common/ad_rst.v \
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$ad_hdl_dir/library/common/ad_axis_inf_rx.v \
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$ad_hdl_dir/library/util_cdc/sync_gray.v \
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util_adcfifo.v \
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util_adcfifo_constr.sdc]
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter FPGA_TECHNOLOGY INTEGER 1
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ad_ip_parameter ADC_DATA_WIDTH INTEGER 256
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ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
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ad_ip_parameter DMA_READY_ENABLE INTEGER 1
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ad_ip_parameter DMA_ADDRESS_WIDTH INTEGER 10
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# elaborate
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proc p_util_adcfifo {} {
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# read parameters
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set m_device_family [get_parameter_value "DEVICE_FAMILY"]
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set m_adc_data_width [get_parameter_value "ADC_DATA_WIDTH"]
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set m_dma_addr_width [get_parameter_value "DMA_ADDRESS_WIDTH"]
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set m_dma_data_width [get_parameter_value "DMA_DATA_WIDTH"]
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# intel memory
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add_hdl_instance mem_asym intel_mem_asym 1.0
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set_instance_parameter_value mem_asym DEVICE_FAMILY $m_device_family
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set_instance_parameter_value mem_asym A_ADDRESS_WIDTH 0
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set_instance_parameter_value mem_asym A_DATA_WIDTH $m_adc_data_width
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set_instance_parameter_value mem_asym B_ADDRESS_WIDTH $m_dma_addr_width
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set_instance_parameter_value mem_asym B_DATA_WIDTH $m_dma_data_width
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# interfaces
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ad_interface clock adc_clk input 1
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ad_interface reset adc_rst input 1 if_adc_clk
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ad_interface signal adc_wr input 1 valid
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ad_interface signal adc_wdata input ADC_DATA_WIDTH data
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ad_interface signal adc_wovf output 1 ovf
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ad_interface clock dma_clk input 1 clk
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ad_interface signal dma_xfer_req input 1 xfer_req
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ad_interface signal dma_xfer_status output 4 xfer_status
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add_interface m_axis axi4stream start
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set_interface_property m_axis associatedClock if_dma_clk
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set_interface_property m_axis associatedReset if_adc_rst
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add_interface_port m_axis dma_wr tvalid Output 1
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add_interface_port m_axis dma_wready tready Input 1
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add_interface_port m_axis dma_wdata tdata Output DMA_DATA_WIDTH
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}
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