285 lines
8.2 KiB
Verilog
Executable File
285 lines
8.2 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_data_in #(
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parameter SINGLE_ENDED = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter DDR_SDR_N = 1,
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parameter IDDR_CLK_EDGE ="SAME_EDGE",
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// for 7 series devices
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parameter IDELAY_TYPE = "VAR_LOAD",
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// for ultrascale devices
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parameter DELAY_FORMAT = "COUNT",
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parameter US_DELAY_TYPE = "VAR_LOAD",
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// for all
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parameter IODELAY_ENABLE = 1,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group",
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parameter REFCLK_FREQUENCY = 200
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) (
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// data interface
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input rx_clk,
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input rx_data_in_p,
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input rx_data_in_n,
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output rx_data_p,
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output rx_data_n,
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// delay-data interface
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input up_clk,
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input up_dld,
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input [ 4:0] up_dwdata,
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output [ 4:0] up_drdata,
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// delay-cntrl interface
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input delay_clk,
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input delay_rst,
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output delay_locked
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);
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// internal parameters
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localparam NONE = -1;
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localparam SEVEN_SERIES = 1;
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localparam ULTRASCALE = 2;
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localparam ULTRASCALE_PLUS = 3;
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// do not instantiate an IDELAYCTRL if no IDELAY is instantiated
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localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE & IODELAY_CTRL);
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localparam IODELAY_CTRL_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE" :
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(FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
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localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" :
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(FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
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/*
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* For 7 series, IDELAYCTRL is enabled ALWAYS, meaning in the following situations:
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* when IDELAY_TYPE = FIXED
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* when IDELAY_TYPE = VARIABLE
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* when IDELAY_TYPE = VAR_LOAD
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**/
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/*
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* For UltraScale/UltraScale+:
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* when DELAY_FORMAT = TIME:
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* IDELAYCTRL must be used
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* REFCLK_FREQUENCY must reflect the clock frequency of REF_CLK applied to
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the IDELAYCTRL component
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* DELAY_VALUE attribute represents an amount in ps
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* The total delay through the IDELAYE3 is the align delay + DELAY_VALUE
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* EN_VTC depends on DELAY_TYPE attribute:
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* when FIXED mode: EN_VTC = 1
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* It must be actively manipulated when the delay line is used in
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VARIABLE or VAR_LOAD mode
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(this section is NOT IMPLEMENTED! More details in UG571, DELAY_TYPE = VAR_LOAD mode and VARIABLE mode)
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* when DELAY_FORMAT = COUNT:
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* DO NOT use an IDELAYCTRL
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* REFCLK_FREQUENCY must be set to default frequency (300MHz)
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* Delay line represents an amount of taps (512 taps available)
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* CNTVALUEIN/OUT[8:0] values represent the amount of taps the delay line
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is set to
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* EN_VTC = 0
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**/
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// internal signals
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wire rx_data_ibuf_s;
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wire rx_data_idelay_s;
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wire [ 8:0] up_drdata_s;
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// internal registers
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reg en_vtc;
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// determine EN_VTC (VAR_LOAD and VARIABLE modes not implemented as in UG571)
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always @(posedge rx_clk) begin
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if (DELAY_FORMAT == "TIME") begin
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if (US_DELAY_TYPE == "FIXED") begin
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en_vtc <= 1'b1;
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end else begin // "VAR_LOAD", "VARIABLE"
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en_vtc <= ~up_dld;
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end
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end else begin // "COUNT"
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en_vtc <= 1'b0;
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end
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end
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// delay controller
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generate
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if (IODELAY_CTRL_ENABLED == 0) begin
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assign delay_locked = 1'b1;
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end else begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYCTRL #(
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.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)
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) i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end
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endgenerate
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// receive data interface, ibuf -> idelay -> iddr(if enabled)
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// ibuf
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generate
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if (SINGLE_ENDED == 1) begin
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IBUF i_rx_data_ibuf (
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.I (rx_data_in_p),
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.O (rx_data_ibuf_s));
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end else begin
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IBUFDS i_rx_data_ibuf (
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.I (rx_data_in_p),
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.IB (rx_data_in_n),
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.O (rx_data_ibuf_s));
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end
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endgenerate
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// bypass IDELAY
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generate
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if (IODELAY_ENABLE == 0) begin
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assign rx_data_idelay_s = rx_data_ibuf_s;
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assign up_drdata = 5'd0;
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end
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endgenerate
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// idelay
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generate
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if (FPGA_TECHNOLOGY == SEVEN_SERIES && IODELAY_ENABLE == 1) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE (IDELAY_TYPE),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA")
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) i_rx_data_idelay (
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.CE (1'b0),
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.INC (1'b0),
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.DATAIN (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (up_clk),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.LD (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata));
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end
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endgenerate
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generate
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if ((FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS)
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&& (IODELAY_ENABLE == 1)) begin
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assign up_drdata = up_drdata_s[8:4];
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE3 #(
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.SIM_DEVICE (IODELAY_SIM_DEVICE),
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.DELAY_SRC ("IDATAIN"),
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.DELAY_TYPE (US_DELAY_TYPE),
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.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
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.DELAY_FORMAT (DELAY_FORMAT)
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) i_rx_data_idelay (
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.CASC_RETURN (1'b0),
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.CASC_IN (1'b0),
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.CASC_OUT (),
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.CE (1'b0),
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.CLK (up_clk),
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.INC (1'b0),
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.LOAD (up_dld),
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.CNTVALUEIN ({up_dwdata, 4'd0}),
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.CNTVALUEOUT (up_drdata_s),
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.DATAIN (1'b0),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.RST (1'b0),
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.EN_VTC (en_vtc));
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end
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endgenerate
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// DDR or SDR
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generate
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if (DDR_SDR_N == 1'b1) begin
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// iddr
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if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
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IDDRE1 #(
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.DDR_CLK_EDGE (IDDR_CLK_EDGE)
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) i_rx_data_iddr (
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.R (1'b0),
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.C (rx_clk),
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.CB (~rx_clk),
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.D (rx_data_idelay_s),
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.Q1 (rx_data_p),
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.Q2 (rx_data_n));
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end
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if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
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IDDR #(
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.DDR_CLK_EDGE (IDDR_CLK_EDGE)
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) i_rx_data_iddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (rx_clk),
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.D (rx_data_idelay_s),
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.Q1 (rx_data_p),
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.Q2 (rx_data_n));
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end
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// sdr
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end else begin
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assign rx_data_p = rx_data_idelay_s;
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assign rx_data_n = 1'b0;
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end
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endgenerate
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endmodule
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