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Add an additional new read only register at 0x03 address for the interface type. This way the software can verify the actual interface mode. |
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README.md
#HDL Reference Designs
Analog Devices HDL libraries and projects
###Tools version:
- Xilinx : Vivado 2015.2.1
- Altera : Quartus 15.0
###Documentation and support
For first time users, it is highly recommended to go through our HDL user guide.
For support please visit our FPGA Reference Designs Support Community on EngineerZone.