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Istvan Csomortani 598ece4c8d axi_ad9361/tdd: Update tdd related logic 
+ TDD pointers and counter width is 24
+ Change TDD control ports name to 'enable' and 'txnrx'
+ Fix constraints
+ Rx or Tx only mode is controlled by a mode enable and a operation mode specifier bit
 		2015-05-21 13:39:48 +03:00
library axi_ad9361/tdd: Update tdd related logic 2015-05-21 13:39:48 +03:00
projects axi_ad9361/tdd: Update tdd related logic 2015-05-21 13:39:48 +03:00
.gitignore gitignore: add non-project stuff 2015-05-01 13:17:14 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md Update README.md 2015-05-20 17:38:08 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

##NOTE

Beware! This branch is just a realease candidate. Final release expected at end of June.

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.