167 lines
6.6 KiB
Verilog
167 lines
6.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module avl_adxcfg (
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// reconfig sharing
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input rcfg_clk,
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input rcfg_reset_n,
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input rcfg_in_read_0,
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input rcfg_in_write_0,
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input [ 9:0] rcfg_in_address_0,
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input [31:0] rcfg_in_writedata_0,
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output [31:0] rcfg_in_readdata_0,
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output rcfg_in_waitrequest_0,
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input rcfg_in_read_1,
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input rcfg_in_write_1,
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input [ 9:0] rcfg_in_address_1,
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input [31:0] rcfg_in_writedata_1,
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output [31:0] rcfg_in_readdata_1,
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output rcfg_in_waitrequest_1,
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output rcfg_out_read_0,
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output rcfg_out_write_0,
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output [ 9:0] rcfg_out_address_0,
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output [31:0] rcfg_out_writedata_0,
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input [31:0] rcfg_out_readdata_0,
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input rcfg_out_waitrequest_0,
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output rcfg_out_read_1,
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output rcfg_out_write_1,
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output [ 9:0] rcfg_out_address_1,
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output [31:0] rcfg_out_writedata_1,
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input [31:0] rcfg_out_readdata_1,
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input rcfg_out_waitrequest_1);
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// internal registers
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reg [ 1:0] rcfg_select = 'd0;
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reg rcfg_read_int = 'd0;
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reg rcfg_write_int = 'd0;
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reg [ 9:0] rcfg_address_int = 'd0;
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reg [31:0] rcfg_writedata_int = 'd0;
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reg [31:0] rcfg_readdata_int = 'd0;
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reg rcfg_waitrequest_int_0 = 'd1;
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reg rcfg_waitrequest_int_1 = 'd1;
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// internal signals
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wire [31:0] rcfg_readdata_s;
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wire rcfg_waitrequest_s;
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// xcvr sharing requires same bus (sw must make sure they are mutually exclusive access).
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assign rcfg_out_read_0 = rcfg_read_int;
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assign rcfg_out_write_0 = rcfg_write_int;
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assign rcfg_out_address_0 = rcfg_address_int;
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assign rcfg_out_writedata_0 = rcfg_writedata_int;
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assign rcfg_out_read_1 = rcfg_read_int;
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assign rcfg_out_write_1 = rcfg_write_int;
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assign rcfg_out_address_1 = rcfg_address_int;
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assign rcfg_out_writedata_1 = rcfg_writedata_int;
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assign rcfg_in_readdata_0 = rcfg_readdata_int;
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assign rcfg_in_readdata_1 = rcfg_readdata_int;
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assign rcfg_in_waitrequest_0 = rcfg_waitrequest_int_0;
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assign rcfg_in_waitrequest_1 = rcfg_waitrequest_int_1;
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assign rcfg_readdata_s = rcfg_out_readdata_1 & rcfg_out_readdata_0;
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assign rcfg_waitrequest_s = rcfg_out_waitrequest_1 & rcfg_out_waitrequest_0;
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always @(negedge rcfg_reset_n or posedge rcfg_clk) begin
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if (rcfg_reset_n == 0) begin
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rcfg_select <= 2'd0;
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rcfg_read_int <= 1'd0;
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rcfg_write_int <= 1'd0;
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rcfg_address_int <= 10'd0;
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rcfg_writedata_int <= 32'd0;
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rcfg_readdata_int = 32'd0;
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rcfg_waitrequest_int_0 <= 1'b1;
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rcfg_waitrequest_int_1 <= 1'b1;
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end else begin
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if (rcfg_select[1] == 1'b1) begin
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if (rcfg_waitrequest_s == 1'b0) begin
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rcfg_select <= 2'd0;
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rcfg_read_int <= 1'b0;
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rcfg_write_int <= 1'b0;
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rcfg_address_int <= 10'd0;
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rcfg_writedata_int <= 32'd0;
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end
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rcfg_readdata_int = rcfg_readdata_s;
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rcfg_waitrequest_int_0 <= rcfg_waitrequest_s | rcfg_select[0];
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rcfg_waitrequest_int_1 <= rcfg_waitrequest_s | ~rcfg_select[0];
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end else if ((rcfg_in_read_0 == 1'b1) || (rcfg_in_write_0 == 1'b1)) begin
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rcfg_select <= 2'b10;
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rcfg_read_int <= rcfg_in_read_0;
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rcfg_write_int <= rcfg_in_write_0;
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rcfg_address_int <= rcfg_in_address_0;
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rcfg_writedata_int <= rcfg_in_writedata_0;
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rcfg_readdata_int = 32'd0;
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rcfg_waitrequest_int_0 <= 1'b1;
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rcfg_waitrequest_int_1 <= 1'b1;
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end else if ((rcfg_in_read_1 == 1'b1) || (rcfg_in_write_1 == 1'b1)) begin
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rcfg_select <= 2'b11;
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rcfg_read_int <= rcfg_in_read_1;
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rcfg_write_int <= rcfg_in_write_1;
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rcfg_address_int <= rcfg_in_address_1;
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rcfg_writedata_int <= rcfg_in_writedata_1;
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rcfg_readdata_int = 32'd0;
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rcfg_waitrequest_int_0 <= 1'b1;
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rcfg_waitrequest_int_1 <= 1'b1;
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end else begin
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rcfg_select <= 2'd0;
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rcfg_read_int <= 1'd0;
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rcfg_write_int <= 1'd0;
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rcfg_address_int <= 10'd0;
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rcfg_writedata_int <= 32'd0;
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rcfg_readdata_int = 32'd0;
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rcfg_waitrequest_int_0 <= 1'b1;
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rcfg_waitrequest_int_1 <= 1'b1;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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