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ad_addsub.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_axi_ip_constr.sdc
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library- altera power up warnings
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2016-12-20 16:18:15 -05:00 |
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ad_axi_ip_constr.xdc
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axi_ip_constr: Fix constraints
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2017-02-27 16:25:09 +02:00 |
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ad_axis_inf_rx.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_csc_1.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_csc_1_add.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_csc_1_mul.v
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library: Fixed changes related to parameters
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2015-08-20 18:13:54 +03:00 |
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ad_csc_CrYCb2RGB.v
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imageon_zc706: Updates and fixes
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2015-03-27 18:57:32 +02:00 |
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ad_csc_RGB2CrYCb.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_datafmt.v
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common- adc- data path disable split
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2016-09-23 13:40:35 -04:00 |
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ad_dcfilter.v
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common- adc- data path disable split
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2016-09-23 13:40:35 -04:00 |
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ad_dds.v
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common- dac data path split
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2016-09-23 16:13:24 -04:00 |
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ad_dds_1.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_dds_sine.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_edge_detect.v
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ad_edge_detect: Add a flop to output, reset is active high
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2015-12-14 15:40:29 +02:00 |
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ad_gt_channel.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_gt_channel_1.v
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up_gt: separate pll resets to tx/rx
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2015-10-02 13:58:30 -04:00 |
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ad_gt_common.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_gt_common_1.v
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up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address
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2015-09-29 14:19:52 +03:00 |
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ad_gt_es.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_gt_es_axi.v
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axi_jesd_gt- per lane split-up
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2015-08-13 13:03:51 -04:00 |
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ad_iqcor.v
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common- adc- data path disable split
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2016-09-23 13:40:35 -04:00 |
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ad_jesd_align.v
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jesd-align-- xilinx/altera merge
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2015-07-21 10:57:00 -04:00 |
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ad_mem.v
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library: forced ad_mem module to be implemented in BRAM for Xilinx devices
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2017-01-25 18:12:04 +02:00 |
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ad_mem_asym.v
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ad_mem_asym: Add support for more ratios.
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2016-04-19 11:18:30 +03:00 |
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ad_pnmon.v
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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ad_rst.v
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library: ad_rst, added comment so that the registers are not minimized away
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2015-11-24 10:33:38 +02:00 |
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ad_ss_422to444.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_ss_444to422.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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ad_sysref_gen.v
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ad_sysref_gen: Fix sysref generation
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2016-12-19 18:02:49 +02:00 |
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ad_tdd_control.v
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ad_tdd_control: Add an on/off switch to the receive datapath
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2016-08-01 11:49:27 +03:00 |
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ad_xcvr_rx_if.v
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library/common- xcvr interface logic
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2016-07-21 16:09:33 -04:00 |
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axi_ctrlif.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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axi_streaming_dma_rx_fifo.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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axi_streaming_dma_tx_fifo.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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dma_fifo.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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pl330_dma_fifo.vhd
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Add .gitattributes file
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2015-06-26 11:07:10 +02:00 |
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sync_bits.v
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all: Change tab to double space
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2016-10-01 18:13:42 +03:00 |
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sync_gray.v
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all: Change tab to double space
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2016-10-01 18:13:42 +03:00 |
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up_adc_channel.v
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common- adc- data path disable split
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2016-09-23 13:40:35 -04:00 |
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up_adc_common.v
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library- altera power up warnings
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2016-12-20 16:18:15 -05:00 |
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up_axi.v
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up_axi- writes dropped by delayed w-responses
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2016-08-14 11:21:19 -04:00 |
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up_clkgen.v
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library: Axi_clkgen, added register for controlling the source clock.
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2015-11-25 11:16:32 +02:00 |
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up_clock_mon.v
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common/up_- change to asynchronous resets
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2015-08-13 13:03:51 -04:00 |
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up_dac_channel.v
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common- dac data path split
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2016-09-23 16:13:24 -04:00 |
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up_dac_common.v
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altera- warnings about init values
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2017-01-30 10:01:28 -05:00 |
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up_delay_cntrl.v
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common- dac data path split
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2016-09-23 16:13:24 -04:00 |
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up_gt.v
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up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address
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2015-09-29 14:19:52 +03:00 |
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up_gt_channel.v
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library/common- reset fix
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2015-10-23 14:32:35 -04:00 |
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up_hdmi_rx.v
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axi_hdmi_rx: Update constraint file and fix reset line
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2015-09-29 18:49:30 +03:00 |
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up_hdmi_tx.v
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all: Change tab to double space
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2016-10-01 18:13:42 +03:00 |
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up_pmod.v
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hdl/library: Update the IP parameters
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2015-08-19 14:11:47 +03:00 |
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up_tdd_cntrl.v
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up_tdd_cntrl: Fix memory map register writes
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2016-11-01 10:06:57 +02:00 |
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up_xfer_cntrl.v
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common/up_- change to asynchronous resets
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2015-08-13 13:03:51 -04:00 |
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up_xfer_status.v
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common/up_- change to asynchronous resets
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2015-08-13 13:03:51 -04:00 |
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util_pulse_gen.v
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common/util_pulse_gen: Rename the ad_tdd_sync module
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2016-06-09 10:07:47 +03:00 |
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