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Istvan Csomortani 5a3c3c878b ad9213_dual_ebz: Initial commit 
Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators
ad9213_dual_ebz/s10soc: Redesign the address layout

avl_peripheral_mm_bridge 0x0000000 0x0001FFFF
  * sys_gpio_in  0x00000000
  * sys_gpio_out 0x00000020
  * sys_spi      0x00000040
  * sys_gpio_bd  0x000000D0
  * sys_id       0x000000E0

avl_mm_bridge_0 0x00040000 0x0007FFFF
  * ad9213_rx_0.phy_reconfig_0     0x00000000
  * ad9213_rx_0.phy_reconfig_1     0x00002000
  * ad9213_rx_0.phy_reconfig_2     0x00004000
  * ad9213_rx_0.phy_reconfig_3     0x00006000
  * ad9213_rx_0.phy_reconfig_4     0x00008000
  * ad9213_rx_0.phy_reconfig_5     0x0000A000
  * ad9213_rx_0.phy_reconfig_6     0x0000C000
  * ad9213_rx_0.phy_reconfig_7     0x0000E000
  * ad9213_rx_0.phy_reconfig_8     0x00010000
  * ad9213_rx_0.phy_reconfig_9     0x00012000
  * ad9213_rx_0.phy_reconfig_10    0x00014000
  * ad9213_rx_0.phy_reconfig_11    0x00016000
  * ad9213_rx_0.phy_reconfig_12    0x00018000
  * ad9213_rx_0.phy_reconfig_13    0x0001A000
  * ad9213_rx_0.phy_reconfig_14    0x0001C000
  * ad9213_rx_0.phy_reconfig_15    0x0001E000
  * ad9213_rx_0.link_pll_reconfig  0x00020000

avl_mm_bridge_1 0x00080000 0x000BFFFF
  * ad9213_rx_1.phy_reconfig_0     0x00000000
  * ad9213_rx_1.phy_reconfig_1     0x00002000
  * ad9213_rx_1.phy_reconfig_2     0x00004000
  * ad9213_rx_1.phy_reconfig_3     0x00006000
  * ad9213_rx_1.phy_reconfig_4     0x00008000
  * ad9213_rx_1.phy_reconfig_5     0x0000A000
  * ad9213_rx_1.phy_reconfig_6     0x0000C000
  * ad9213_rx_1.phy_reconfig_7     0x0000E000
  * ad9213_rx_1.phy_reconfig_8     0x00010000
  * ad9213_rx_1.phy_reconfig_9     0x00012000
  * ad9213_rx_1.phy_reconfig_10    0x00014000
  * ad9213_rx_1.phy_reconfig_11    0x00016000
  * ad9213_rx_1.phy_reconfig_12    0x00018000
  * ad9213_rx_1.phy_reconfig_13    0x0001A000
  * ad9213_rx_1.phy_reconfig_14    0x0001C000
  * ad9213_rx_1.phy_reconfig_15    0x0001E000
  * ad9213_rx_1.link_pll_reconfig  0x00020000

Connected directly to the h2s_lw_axi_master
  * ad9213_rx_0.link_reconfig      0x000C0000
  * ad9213_rx_0.link_management    0x000C4000
  * ad9213_rx_1.link_reconfig      0x000C8000
  * ad9213_rx_1.link_management    0x000CC000
  * axi_ad9213_0.s_axi             0x000D0000
  * axi_ad9213_1.s_axi             0x000D1000
  * axi_ad9213_dma_0.s_axi         0x000D2000
  * axi_ad9213_dma_1.s_axi         0x000D3800
 		2021-09-30 17:40:13 +03:00
.github/ISSUE_TEMPLATE template: Add a bug report and feature request template 2019-09-04 16:22:14 +03:00
docs HDL Logo: Add 2021-09-16 16:49:52 +03:00
library data_offload: Fix oversized inputs in TX mode 2021-09-29 18:33:11 +03:00
projects ad9213_dual_ebz: Initial commit 2021-09-30 17:40:13 +03:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore .gitignore: add simulation outputs and misc files to the list 2019-11-26 13:43:22 +02:00
LICENSE Make system: Be explicit in license that cover the make/build system 2021-09-16 16:50:53 +03:00
LICENSE_ADIBSD Make system: Be explicit in license that cover the make/build system 2021-09-16 16:50:53 +03:00
LICENSE_BSD-1-Clause Make system: Be explicit in license that cover the make/build system 2021-09-16 16:50:53 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL License: Update LGPL to version 2.1 2020-03-06 16:07:18 +02:00
Makefile Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
README.md README.md: State the main purpose of the repository 2019-08-26 16:32:23 +03:00
quiet.mk Make system: Be explicit in license that cover the make/build system 2021-09-16 16:50:53 +03:00

README.md

HDL Reference Designs

Analog Devices Inc. HDL libraries and projects for various reference design and prototyping systems. This repository contains HDL code (Verilog or VHDL) and the required Tcl scripts to create and build a specific FPGA example design using Xilinx and/or Intel tool chain.

Support

The HDL is provided "AS IS", support is only provided on EngineerZone.

If you feel you can not, or do not want to ask questions on EngineerZone, you should not use or look at the HDL found in this repository. Just like you have the freedom and rights to use this software in your products (with the obligations found in individual licenses) and get support on EngineerZone, you have the freedom and rights not to use this software and get datasheet level support from traditional ADI contacts that you may have.

There is no free replacement for consulting services. If you have questions that are best handed one-on-one engagement, and are time sensitive, consider hiring a consultant. If you want to find a consultant who is familar with the HDL found in this repository - ask on EngineerZone.

Getting started

This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.

Prerequisites

or

Please make sure that you have the required tool version.

How to build a project

For building a project (generate a bitstream), you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.

To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:

 [~]cd projects/fmcomms2/zc706
 [~]make

A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build

Software

In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.

Which branch should I use?

  • If you want to use the most stable code base, always use the latest release branch.

  • If you want to use the greatest and latest, check out the master branch.

License

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

See LICENSE for more details. The separate license files cab be found here:

Comprehensive user guide

See HDL User Guide for a more detailed guide.