Rejeesh Kutty 56ddce1e8c dmac: create fifo interface to avoid being treated as axi control stream		2014-05-27 10:25:14 -04:00
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zc706_system_bd.tcl	Zynq Base System: Reset is synchronized to lowest system clock	2014-03-26 17:58:14 +02:00
zc706_system_constr.xdc	added common board files	2014-02-28 21:17:01 -05:00
zc706_system_mig.prj	zc706: added pl ddr3 mig	2014-04-09 15:58:12 -04:00
zc706_system_mig_constr.xdc	dmac: create fifo interface to avoid being treated as axi control stream	2014-05-27 10:25:14 -04:00
zc706_system_plddr3.tcl	zc706: pl ddr3 initial checkin	2014-05-13 16:19:53 -04:00