216 lines
6.8 KiB
Verilog
216 lines
6.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_clkgen (
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// mmcm reset
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mmcm_rst,
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// drp interface
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drp_clk,
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drp_rst,
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drp_sel,
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drp_wr,
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drp_addr,
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drp_wdata,
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drp_rdata,
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drp_ready,
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drp_locked,
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// bus interface
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up_rstn,
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up_clk,
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up_sel,
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up_wr,
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up_addr,
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up_wdata,
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up_rdata,
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up_ack);
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// parameters
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parameter PCORE_VERSION = 32'h00040062;
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parameter PCORE_ID = 0;
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// mmcm reset
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output mmcm_rst;
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// drp interface
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input drp_clk;
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output drp_rst;
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output drp_sel;
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output drp_wr;
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output [11:0] drp_addr;
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output [15:0] drp_wdata;
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input [15:0] drp_rdata;
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input drp_ready;
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input drp_locked;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_sel;
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input up_wr;
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input [13:0] up_addr;
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input [31:0] up_wdata;
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output [31:0] up_rdata;
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output up_ack;
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// internal registers
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reg [31:0] up_scratch = 'd0;
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reg up_mmcm_resetn = 'd0;
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reg up_resetn = 'd0;
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reg up_drp_sel_t = 'd0;
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reg up_drp_rwn = 'd0;
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reg [11:0] up_drp_addr = 'd0;
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reg [15:0] up_drp_wdata = 'd0;
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reg up_ack = 'd0;
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reg [31:0] up_rdata = 'd0;
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// internal signals
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wire up_sel_s;
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wire up_wr_s;
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wire up_preset_s;
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wire up_mmcm_preset_s;
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wire [15:0] up_drp_rdata_s;
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wire up_drp_status_s;
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wire up_drp_locked_s;
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// decode block select
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assign up_sel_s = (up_addr[13:8] == 6'h00) ? up_sel : 1'b0;
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assign up_wr_s = up_sel_s & up_wr;
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assign up_preset_s = ~up_resetn;
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assign up_mmcm_preset_s = ~up_mmcm_resetn;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_scratch <= 'd0;
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up_mmcm_resetn <= 'd0;
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up_resetn <= 'd0;
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up_drp_sel_t <= 'd0;
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up_drp_rwn <= 'd0;
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up_drp_addr <= 'd0;
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up_drp_wdata <= 'd0;
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end else begin
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if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h10)) begin
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up_mmcm_resetn <= up_wdata[1];
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up_resetn <= up_wdata[0];
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end
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if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h1c)) begin
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up_drp_sel_t <= ~up_drp_sel_t;
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up_drp_rwn <= up_wdata[28];
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up_drp_addr <= up_wdata[27:16];
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up_drp_wdata <= up_wdata[15:0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_ack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_ack <= up_sel_s;
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if (up_sel_s == 1'b1) begin
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case (up_addr[7:0])
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8'h00: up_rdata <= PCORE_VERSION;
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8'h01: up_rdata <= PCORE_ID;
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8'h02: up_rdata <= up_scratch;
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8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
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8'h17: up_rdata <= {31'd0, up_drp_locked_s};
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8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
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8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s};
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// resets
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ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(drp_clk), .rst(mmcm_rst));
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ad_rst i_drp_rst_reg (.preset(up_preset_s), .clk(drp_clk), .rst(drp_rst));
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// drp control & status
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up_drp_cntrl i_drp_cntrl (
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.drp_clk (drp_clk),
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.drp_rst (drp_rst),
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.drp_sel (drp_sel),
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.drp_wr (drp_wr),
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.drp_addr (drp_addr),
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.drp_wdata (drp_wdata),
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.drp_rdata (drp_rdata),
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.drp_ready (drp_ready),
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.drp_locked (drp_locked),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_drp_sel_t (up_drp_sel_t),
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.up_drp_rwn (up_drp_rwn),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata),
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.up_drp_rdata (up_drp_rdata_s),
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.up_drp_status (up_drp_status_s),
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.up_drp_locked (up_drp_locked_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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