Adrian Costina 215edb11c6 adrv9371: A10GX, updated design ... - disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point - update FIFO SIZE to 16 for all DMAs - updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.		2016-08-23 18:25:48 +03:00
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adrv9371x_bd.qsys	adrv9371x/a10soc: Export axi_ad9371_s and xcvr_reconfig_avmm	2016-08-17 19:03:53 +03:00
adrv9371x_bd.tcl	adrv9371x: Updated project common	2016-08-22 16:58:21 +03:00
adrv9371x_qsys.tcl	adrv9371: A10GX, updated design	2016-08-23 18:25:48 +03:00