Adrian Costina ee0617661e axi_ad9680: Updated altera interfaces, added FIFO conduits per channel		2015-11-24 11:45:12 +02:00
..
Makefile	Makefile: Update Make files	2015-07-03 18:08:57 +03:00
axi_ad9680.v	axi_ad9680: Clock ratio is indicating a sampling clock ratio	2015-09-24 11:19:29 +03:00
axi_ad9680_channel.v	hdl/library: Update the IP parameters	2015-08-19 14:11:47 +03:00
axi_ad9680_constr.xdc	library: make preset registered for timing paths	2015-06-10 13:41:41 -04:00
axi_ad9680_hw.tcl	axi_ad9680: Updated altera interfaces, added FIFO conduits per channel	2015-11-24 11:45:12 +02:00
axi_ad9680_if.v	Add .gitattributes file	2015-06-26 11:07:10 +02:00
axi_ad9680_ip.tcl	Revert commit 6b99ce	2015-08-26 13:48:28 +03:00
axi_ad9680_pnmon.v	Add .gitattributes file	2015-06-26 11:07:10 +02:00