276 lines
10 KiB
Verilog
276 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_dacfifo_bypass #(
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parameter DAC_DATA_WIDTH = 64,
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parameter DMA_DATA_WIDTH = 64) (
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// dma fifo interface
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input dma_clk,
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input [(DMA_DATA_WIDTH-1):0] dma_data,
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input dma_ready,
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output reg dma_ready_out,
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input dma_valid,
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// request and syncronizaiton
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input dma_xfer_req,
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// dac fifo interface
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input dac_clk,
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input dac_rst,
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input dac_valid,
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output reg [(DAC_DATA_WIDTH-1):0] dac_data,
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output reg dac_dunf
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);
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// suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
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localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH :
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DAC_DATA_WIDTH/DMA_DATA_WIDTH;
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localparam DAC_ADDRESS_WIDTH = 10;
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localparam DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :
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(MEM_RATIO == 2) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 1) : (DAC_ADDRESS_WIDTH + 1)) :
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(MEM_RATIO == 4) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH + 2)) :
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((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 3) : (DAC_ADDRESS_WIDTH + 3));
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localparam DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4;
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localparam DAC_BUF_THRESHOLD_LO = 4;
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reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0;
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reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0;
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reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0;
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reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0;
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reg dac_mem_rea = 1'b0;
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reg dac_mem_rea_d = 1'b0;
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reg dma_rst_m1 = 1'b0;
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reg dma_rst = 1'b0;
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reg [DMA_ADDRESS_WIDTH-1:0] dma_mem_addr_diff = 1'b0;
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reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 1'b0;
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reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 1'b0;
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reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr = 1'b0;
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reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 1'b0;
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reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 1'b0;
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reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr = 1'b0;
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reg dac_xfer_out = 1'b0;
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reg dac_xfer_out_m1 = 1'b0;
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// internal signals
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wire [(DAC_ADDRESS_WIDTH):0] dac_mem_addr_diff_s;
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wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_raddr_s;
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wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_s;
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wire dma_mem_wea_s;
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wire dac_mem_rea_s;
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wire [(DAC_DATA_WIDTH-1):0] dac_mem_rdata_s;
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wire [DMA_ADDRESS_WIDTH:0] dma_address_diff_s;
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wire dac_mem_empty_s;
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wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s;
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wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s;
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wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;
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wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
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// An asymmetric memory to transfer data from DMAC interface to DAC interface
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alt_mem_asym_bypass i_mem_asym (
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.mem_i_wrclock (dma_clk),
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.mem_i_wren (dma_mem_wea_s),
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.mem_i_wraddress (dma_mem_waddr),
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.mem_i_datain (dma_data),
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.mem_i_rdclock (dac_clk),
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.mem_i_rdaddress (dac_mem_raddr),
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.mem_o_dataout (dac_mem_rdata_s));
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// dma reset is brought from dac domain
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always @(posedge dma_clk) begin
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dma_rst_m1 <= dac_rst;
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dma_rst <= dma_rst_m1;
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end
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// Write address generation for the asymmetric memory
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assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
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always @(posedge dma_clk) begin
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if (dma_rst == 1'b1) begin
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dma_mem_waddr <= 'h0;
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dma_mem_waddr_g <= 'h0;
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end else begin
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if (dma_mem_wea_s == 1'b1) begin
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dma_mem_waddr <= dma_mem_waddr + 1'b1;
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end
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dma_mem_waddr_g <= dma_mem_waddr_b2g_s;
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end
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end
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ad_b2g #(
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.DATA_WIDTH (DMA_ADDRESS_WIDTH))
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i_dma_mem_waddr_b2g (
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.din (dma_mem_waddr),
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.dout (dma_mem_waddr_b2g_s));
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// The memory module request data until reaches the high threshold.
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always @(posedge dma_clk) begin
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if (dma_rst == 1'b1) begin
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dma_mem_addr_diff <= 'b0;
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dma_mem_raddr_m1 <= 'b0;
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dma_mem_raddr_m2 <= 'b0;
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dma_mem_raddr <= 'b0;
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dma_ready_out <= 1'b0;
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end else begin
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dma_mem_raddr_m1 <= dac_mem_raddr_g;
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dma_mem_raddr_m2 <= dma_mem_raddr_m1;
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dma_mem_raddr <= dma_mem_raddr_m2_g2b_s;
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dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0];
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if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
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dma_ready_out <= 1'b0;
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end else begin
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dma_ready_out <= 1'b1;
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end
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end
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end
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ad_g2b #(
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.DATA_WIDTH (DAC_ADDRESS_WIDTH))
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i_dma_mem_raddr_g2b (
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.din (dma_mem_raddr_m2),
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.dout (dma_mem_raddr_m2_g2b_s));
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// relative address offset on dma domain
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assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
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assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
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((MEM_RATIO == 1) ? (dma_mem_raddr) :
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(MEM_RATIO == 2) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):1]) :
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(MEM_RATIO == 4) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):2]) : (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):3])) :
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((MEM_RATIO == 1) ? (dma_mem_raddr) :
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(MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) :
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(MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0}));
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// relative address offset on dac domain
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assign dac_address_diff_s = {1'b1, dac_mem_waddr_s} - dac_mem_raddr;
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assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ?
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((MEM_RATIO == 1) ? (dac_mem_waddr) :
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(MEM_RATIO == 2) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):1]) :
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(MEM_RATIO == 4) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):2]) : (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):3])) :
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((MEM_RATIO == 1) ? (dac_mem_waddr) :
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(MEM_RATIO == 2) ? ({dac_mem_waddr, 1'b0}) :
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(MEM_RATIO == 4) ? ({dac_mem_waddr, 2'b0}) : ({dac_mem_waddr, 3'b0}));
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// Read address generation for the asymmetric memory
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assign dac_mem_empty_s = (dac_mem_waddr_s == dac_mem_raddr) ? 1'b1 : 1'b0;
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assign dac_mem_rea_s = dac_valid & !dac_mem_empty_s;
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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dac_mem_raddr <= 'h0;
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dac_mem_raddr_g <= 'h0;
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end else begin
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if (dac_mem_rea_s == 1'b1) begin
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dac_mem_raddr <= dac_mem_raddr + 1'b1;
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end
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dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
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end
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end
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// compensate the read latency of the memory
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always @(posedge dac_clk) begin
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dac_mem_rea_d <= dac_mem_rea_s;
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dac_mem_rea <= dac_mem_rea_d;
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end
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ad_b2g #(
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.DATA_WIDTH (DAC_ADDRESS_WIDTH))
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i_dac_mem_raddr_b2g (
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.din (dac_mem_raddr),
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.dout (dac_mem_raddr_b2g_s));
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// The memory module is ready if it's not empty
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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dac_mem_waddr_m1 <= 'b0;
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dac_mem_waddr_m2 <= 'b0;
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dac_mem_waddr <= 'b0;
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end else begin
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dac_mem_waddr_m1 <= dma_mem_waddr_g;
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dac_mem_waddr_m2 <= dac_mem_waddr_m1;
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dac_mem_waddr <= dac_mem_waddr_m2_g2b_s;
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end
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end
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ad_g2b #(
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.DATA_WIDTH (DMA_ADDRESS_WIDTH))
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i_dac_mem_waddr_g2b (
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.din (dac_mem_waddr_m2),
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.dout (dac_mem_waddr_m2_g2b_s));
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// define underflow
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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dac_xfer_out_m1 <= 1'b0;
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dac_xfer_out <= 1'b0;
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dac_dunf <= 1'b0;
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end else begin
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dac_xfer_out_m1 <= dma_xfer_req;
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dac_xfer_out <= dac_xfer_out_m1;
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if (dac_valid == 1'b1) begin
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dac_dunf <= dac_mem_empty_s;
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end
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end
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end
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// DAC data output logic
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always @(posedge dac_clk) begin
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if (dac_dunf == 1'b1) begin
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dac_data <= 0;
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end else begin
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dac_data <= dac_mem_rdata_s;
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end
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end
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endmodule
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