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Lars-Peter Clausen 5dcdc5198b ad_ip_jesd204_dac_tpl: hw.tcl: Add framer input information parameters
The exact layout of the input data into the DAC transport layer core
depends on the framer configuration. The number of input channels is
always equal to the NUM_CHANNELS parameter, but the number of samples per
channel per beat depends on the ratio of number of lanes, number of
channels and bits per sample.

It is possible to compute this manually, but this might require in-depth
knowledge about how the JESD204 framer works. Add read-only parameters that
display the number of samples per channel per beat as well as the total
width of the channel data signal.

This information can also be queried in QSys scripts and used to
automatically configure the input pipeline. E.g. like the upack core:

  set NUM_OF_CHANNELS  [get_instance_parameter_value jesd204_transport NUM_CHANNELS]
  set CHANNEL_DATA_WIDTH [get_instance_parameter_value jesd204_transport CHANNEL_DATA_WIDTH]

  add_instance util_dac_upack util_upack
  set_instance_parameter_values util_dac_upack [list \
    CHANNEL_DATA_WIDTH $CHANNEL_DATA_WIDTH \
    NUM_OF_CHANNELS $NUM_OF_CHANNELS \
  ]

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-23 18:35:30 +03:00
library ad_ip_jesd204_dac_tpl: hw.tcl: Add framer input information parameters 2018-08-23 18:35:30 +03:00
projects daq3: ZCU102: Remove Offload FIFO for ADC path. 2018-08-23 18:06:32 +03:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
LICENSE license: GPL must be GPL v2 2017-05-31 18:18:45 +03:00
LICENSE_ADIBSD license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL license: Add top level license files 2017-05-29 09:57:39 +03:00
Makefile Add quiet mode to the Makefile system 2018-04-11 15:09:54 +03:00
README.md README: Remove the Documentation section, it's redundant 2018-03-07 12:28:40 +00:00
quiet.mk quiet.mk: Fix newline generation in error message 2018-04-12 18:19:43 +02:00

README.md

HDL Reference Designs

Analog Devices Inc. HDL libraries and projects.

Getting started

This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.

Prerequisites

or

Please make sure that you have the required tool version.

How to build a project

For building a projects, you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.

To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:

 [~]cd projects/fmcomms2/zc706
 [~]make

A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build

Software

In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.

Which branch should I use?

  • If you want to use the most stable code base, always use the latest release branch.

  • If you want to use the greatest and latest, check out the master branch.

License

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

See LICENSE for more details. The separate license files cab be found here:

Comprehensive user guide

See HDL User Guide for a more detailed guide.

Support

Feel free to ask any question at EngineerZone.