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pluto_hdl_adi/library/jesd204/tb
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Istvan Csomortani 157afcbc33 tb_base: Fix various test benches 
The tb_base.v verilog files does not contain a full module definition,
just some plain test code. In general the files is sourced inside the
test bench main module. As is, defining a timescale in these files will
generate an error, because timescale directive can not be inside a
module.

Delete all the timescale directive from these files.
 		2019-05-17 11:20:48 +03:00
..
.gitignore Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
axi_jesd204_rx_regmap_tb jesd204: axi_jesd204_rx_regmap_tb: Add missing dependency 2017-08-13 10:28:11 +02:00
axi_jesd204_rx_regmap_tb.v jesd204/tb: support for ModelSim and Xsim 2019-01-21 10:33:30 +02:00
axi_jesd204_tx_regmap_tb Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00
axi_jesd204_tx_regmap_tb.v jesd204/tb: support for ModelSim and Xsim 2019-01-21 10:33:30 +02:00
loopback_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
loopback_tb.v jesd204/tb: support for ModelSim and Xsim 2019-01-21 10:33:30 +02:00
run_tb.sh jesd204/tb: support for ModelSim and Xsim 2019-01-21 10:33:30 +02:00
rx_cgs_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
rx_cgs_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
rx_ctrl_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
rx_ctrl_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
rx_lane_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
rx_lane_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
rx_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
rx_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
scrambler_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
scrambler_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
soft_pcs_8b10b_sequence_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
soft_pcs_8b10b_sequence_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
soft_pcs_8b10b_table_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
soft_pcs_8b10b_table_tb.v jesd204/tb: support for ModelSim and Xsim 2019-01-21 10:33:30 +02:00
soft_pcs_loopback_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
soft_pcs_loopback_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
soft_pcs_pattern_align_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
soft_pcs_pattern_align_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
tb_base.v tb_base: Fix various test benches 2019-05-17 11:20:48 +03:00
tx_ctrl_phase_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
tx_ctrl_phase_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
tx_tb jesd204: Update testbench with the new file names 2018-04-11 15:09:54 +03:00
tx_tb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00