pluto_hdl_adi/library/spi_engine
Stanca Pop 5ec87615b0 axi_spi_engine: Fix the SYNC interface
The ready signal of the SYNC interface should be always 1'b1,
regardless of ASYNC_SPI_VALUE.

Drive the ready with one in both branches of the ASYNC_SPI_CLK
generate block.
2019-09-11 16:45:30 +03:00
..
axi_spi_engine axi_spi_engine: Fix the SYNC interface 2019-09-11 16:45:30 +03:00
interfaces spi_engine: Add support for 8 SDI lines 2018-04-11 15:09:54 +03:00
spi_engine_execution library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
spi_engine_interconnect library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
spi_engine_offload library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00