256 lines
8.1 KiB
Verilog
256 lines
8.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This is the LVDS/DDR interface, note that overrange is independent of data path,
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// software will not be able to relate overrange to a specific sample!
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// Alternative is to concatenate sample value and or status for data.
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`timescale 1ns/100ps
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module axi_ad9643_if (
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// adc interface (clk, data, over-range)
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adc_clk_in_p,
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adc_clk_in_n,
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adc_data_in_p,
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adc_data_in_n,
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adc_or_in_p,
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adc_or_in_n,
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// interface outputs
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adc_clk,
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adc_data_a,
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adc_data_b,
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adc_or_a,
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adc_or_b,
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adc_status,
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// processor control signals
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adc_ddr_edgesel,
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adc_pin_mode,
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// delay control signals
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up_clk,
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up_dld,
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up_dwdata,
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up_drdata,
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delay_clk,
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delay_rst,
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delay_locked);
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// This parameter controls the buffer type based on the target device.
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parameter PCORE_BUFTYPE = 0;
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parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
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// adc interface (clk, data, over-range)
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input adc_clk_in_p;
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input adc_clk_in_n;
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input [13:0] adc_data_in_p;
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input [13:0] adc_data_in_n;
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input adc_or_in_p;
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input adc_or_in_n;
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// interface outputs
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output adc_clk;
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output [13:0] adc_data_a;
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output [13:0] adc_data_b;
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output adc_or_a;
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output adc_or_b;
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output adc_status;
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// processor control signals
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input adc_ddr_edgesel;
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input adc_pin_mode;
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// delay control signals
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input up_clk;
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input [14:0] up_dld;
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input [74:0] up_dwdata;
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output [74:0] up_drdata;
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input delay_clk;
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input delay_rst;
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output delay_locked;
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// internal registers
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reg adc_status = 'd0;
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reg [13:0] adc_data_p = 'd0;
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reg [13:0] adc_data_n = 'd0;
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reg [13:0] adc_data_p_d = 'd0;
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reg adc_or_p = 'd0;
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reg adc_or_n = 'd0;
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reg adc_or_p_d = 'd0;
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reg [13:0] adc_data_mux_a = 'd0;
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reg [13:0] adc_data_mux_b = 'd0;
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reg adc_or_mux_a = 'd0;
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reg adc_or_mux_b = 'd0;
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reg [13:0] adc_data_a = 'd0;
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reg [13:0] adc_data_b = 'd0;
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reg adc_or_a = 'd0;
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reg adc_or_b = 'd0;
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// internal signals
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wire [13:0] adc_data_p_s;
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wire [13:0] adc_data_n_s;
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wire adc_or_p_s;
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wire adc_or_n_s;
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genvar l_inst;
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// two data pin modes are supported-
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// mux - across clock edges (rising or falling edges),
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// mux - within clock edges (lower 7 bits and upper 7 bits)
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always @(posedge adc_clk) begin
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adc_status <= 1'b1;
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adc_data_p <= adc_data_p_s;
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adc_data_n <= adc_data_n_s;
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adc_data_p_d <= adc_data_p;
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adc_or_p <= adc_or_p_s;
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adc_or_n <= adc_or_n_s;
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adc_or_p_d <= adc_or_p;
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end
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always @(posedge adc_clk) begin
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if (adc_ddr_edgesel == 1'b1) begin
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adc_data_mux_a <= adc_data_p_d;
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adc_data_mux_b <= adc_data_n;
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adc_or_mux_a <= adc_or_p_d;
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adc_or_mux_b <= adc_or_n;
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end else begin
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adc_data_mux_a <= adc_data_n;
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adc_data_mux_b <= adc_data_p;
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adc_or_mux_a <= adc_or_n;
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adc_or_mux_b <= adc_or_p;
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end
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end
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always @(posedge adc_clk) begin
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if (adc_pin_mode == 1'b1) begin
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adc_data_a <= adc_data_mux_a;
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adc_data_b <= adc_data_mux_b;
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adc_or_a <= adc_or_mux_a;
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adc_or_b <= adc_or_mux_b;
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end else begin
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adc_data_a <= { adc_data_mux_b[13], adc_data_mux_a[13],
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adc_data_mux_b[12], adc_data_mux_a[12],
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adc_data_mux_b[11], adc_data_mux_a[11],
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adc_data_mux_b[10], adc_data_mux_a[10],
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adc_data_mux_b[ 9], adc_data_mux_a[ 9],
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adc_data_mux_b[ 8], adc_data_mux_a[ 8],
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adc_data_mux_b[ 7], adc_data_mux_a[ 7]};
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adc_data_b <= { adc_data_mux_b[ 6], adc_data_mux_a[ 6],
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adc_data_mux_b[ 5], adc_data_mux_a[ 5],
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adc_data_mux_b[ 4], adc_data_mux_a[ 4],
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adc_data_mux_b[ 3], adc_data_mux_a[ 3],
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adc_data_mux_b[ 2], adc_data_mux_a[ 2],
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adc_data_mux_b[ 1], adc_data_mux_a[ 1],
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adc_data_mux_b[ 0], adc_data_mux_a[ 0]};
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adc_or_a <= adc_or_mux_a;
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adc_or_b <= adc_or_mux_b;
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end
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end
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// data interface
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generate
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for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
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ad_lvds_in #(
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.BUFTYPE (PCORE_BUFTYPE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (PCORE_IODELAY_GROUP))
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i_adc_data (
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.rx_clk (adc_clk),
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.rx_data_in_p (adc_data_in_p[l_inst]),
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.rx_data_in_n (adc_data_in_n[l_inst]),
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.rx_data_p (adc_data_p_s[l_inst]),
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.rx_data_n (adc_data_n_s[l_inst]),
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.up_clk (up_clk),
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.up_dld (up_dld[l_inst]),
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.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
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.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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end
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endgenerate
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// over-range interface
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ad_lvds_in #(
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.BUFTYPE (PCORE_BUFTYPE),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (PCORE_IODELAY_GROUP))
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i_adc_or (
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.rx_clk (adc_clk),
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.rx_data_in_p (adc_or_in_p),
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.rx_data_in_n (adc_or_in_n),
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.rx_data_p (adc_or_p_s),
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.rx_data_n (adc_or_n_s),
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.up_clk (up_clk),
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.up_dld (up_dld[14]),
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.up_dwdata (up_dwdata[74:70]),
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.up_drdata (up_drdata[74:70]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked));
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// clock
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ad_lvds_clk #(
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.BUFTYPE (PCORE_BUFTYPE))
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i_adc_clk (
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.clk_in_p (adc_clk_in_p),
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.clk_in_n (adc_clk_in_n),
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.clk (adc_clk));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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