331 lines
9.9 KiB
Verilog
331 lines
9.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_axis_dma_rx (
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// dma interface
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dma_clk,
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dma_rst,
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dma_valid,
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dma_last,
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dma_data,
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dma_ready,
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dma_ovf,
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dma_unf,
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dma_status,
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dma_bw,
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// data interface
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adc_clk,
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adc_rst,
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adc_valid,
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adc_data,
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// processor interface
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dma_start,
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dma_stream,
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dma_count);
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// parameters
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parameter DATA_WIDTH = 64;
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localparam DW = DATA_WIDTH - 1;
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localparam BUF_THRESHOLD_LO = 6'd3;
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localparam BUF_THRESHOLD_HI = 6'd60;
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localparam DATA_WIDTH_IN_BYTES = DATA_WIDTH/8;
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// dma interface
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input dma_clk;
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input dma_rst;
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output dma_valid;
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output dma_last;
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output [DW:0] dma_data;
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input dma_ready;
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output dma_ovf;
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output dma_unf;
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output dma_status;
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output [31:0] dma_bw;
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// data interface
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input adc_clk;
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input adc_rst;
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input adc_valid;
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input [DW:0] adc_data;
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// processor interface
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input dma_start;
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input dma_stream;
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input [31:0] dma_count;
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// internal registers
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reg dma_valid_int = 'd0;
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reg dma_last_int = 'd0;
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reg [DW:0] dma_data_int = 'd0;
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reg dma_capture_enable = 'd0;
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reg [31:0] dma_capture_count = 'd0;
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reg dma_rd = 'd0;
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reg [ 5:0] dma_raddr = 'd0;
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reg dma_release_toggle_m1 = 'd0;
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reg dma_release_toggle_m2 = 'd0;
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reg dma_release_toggle_m3 = 'd0;
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reg [ 5:0] dma_release_waddr = 'd0;
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reg [ 5:0] dma_waddr_m1 = 'd0;
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reg [ 5:0] dma_waddr_m2 = 'd0;
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reg [ 5:0] dma_waddr = 'd0;
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reg [ 5:0] dma_addr_diff = 'd0;
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reg dma_almost_full = 'd0;
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reg dma_almost_empty = 'd0;
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reg dma_ovf = 'd0;
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reg dma_unf = 'd0;
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reg dma_resync = 'd0;
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reg adc_wr = 'd0;
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reg [ 5:0] adc_waddr = 'd0;
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reg [ 5:0] adc_waddr_g = 'd0;
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reg [ 3:0] adc_release_count = 'd0;
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reg [DW:0] adc_wdata = 'd0;
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reg adc_release_toggle = 'd0;
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reg [ 5:0] adc_release_waddr = 'd0;
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reg adc_resync_m1 = 'd0;
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reg adc_resync_m2 = 'd0;
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reg adc_resync = 'd0;
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// internal signals
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wire dma_rd_valid_s;
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wire dma_last_s;
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wire dma_ready_s;
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wire dma_rd_s;
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wire dma_release_s;
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wire [ 6:0] dma_addr_diff_s;
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wire dma_ovf_s;
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wire dma_unf_s;
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wire [DW:0] dma_rdata_s;
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// binary to grey conversion
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function [5:0] b2g;
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input [5:0] b;
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reg [5:0] g;
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begin
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g[5] = b[5];
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g[4] = b[5] ^ b[4];
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g[3] = b[4] ^ b[3];
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g[2] = b[3] ^ b[2];
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g[1] = b[2] ^ b[1];
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g[0] = b[1] ^ b[0];
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b2g = g;
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end
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endfunction
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// grey to binary conversion
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function [5:0] g2b;
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input [5:0] g;
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reg [5:0] b;
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begin
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b[5] = g[5];
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b[4] = b[5] ^ g[4];
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b[3] = b[4] ^ g[3];
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b[2] = b[3] ^ g[2];
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b[1] = b[2] ^ g[1];
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b[0] = b[1] ^ g[0];
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g2b = b;
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end
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endfunction
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// dma read- user interface
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assign dma_bw = DATA_WIDTH_IN_BYTES;
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assign dma_status = dma_capture_enable;
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always @(posedge dma_clk) begin
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dma_valid_int <= dma_rd_valid_s;
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dma_last_int <= dma_last_s;
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dma_data_int <= dma_rdata_s;
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end
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// dma read- capture control signals
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assign dma_rd_valid_s = dma_capture_enable & dma_rd;
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assign dma_last_s = (dma_capture_count == dma_count) ? dma_rd_valid_s : 1'b0;
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always @(posedge dma_clk) begin
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if ((dma_stream == 1'b0) && (dma_last_s == 1'b1)) begin
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dma_capture_enable <= 1'b0;
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end else if (dma_start == 1'b1) begin
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dma_capture_enable <= 1'b1;
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end
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if ((dma_capture_enable == 1'b0) || (dma_last_s == 1'b1)) begin
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dma_capture_count <= dma_bw;
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end else if (dma_rd == 1'b1) begin
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dma_capture_count <= dma_capture_count + dma_bw;
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end
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end
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// dma read- read data always and pass it to the external memory
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assign dma_ready_s = (~dma_capture_enable) | dma_ready;
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assign dma_rd_s = (dma_release_waddr == dma_raddr) ? 1'b0 : dma_ready_s;
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always @(posedge dma_clk) begin
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dma_rd <= dma_rd_s;
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if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin
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dma_raddr <= 6'd0;
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end else if (dma_rd_s == 1'b1) begin
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dma_raddr <= dma_raddr + 1'b1;
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end
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end
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// dma read- get bursts of adc data from the other side
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assign dma_release_s = dma_release_toggle_m3 ^ dma_release_toggle_m2;
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always @(posedge dma_clk) begin
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if (dma_rst == 1'b1) begin
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dma_release_toggle_m1 <= 'd0;
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dma_release_toggle_m2 <= 'd0;
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dma_release_toggle_m3 <= 'd0;
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end else begin
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dma_release_toggle_m1 <= adc_release_toggle;
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dma_release_toggle_m2 <= dma_release_toggle_m1;
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dma_release_toggle_m3 <= dma_release_toggle_m2;
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end
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if (dma_resync == 1'b1) begin
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dma_release_waddr <= 6'd0;
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end else if (dma_release_s == 1'b1) begin
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dma_release_waddr <= adc_release_waddr;
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end
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end
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// dma read- get free running write address for ovf/unf checking
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assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
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assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0;
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assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0;
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always @(posedge dma_clk) begin
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if (dma_rst == 1'b1) begin
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dma_waddr_m1 <= 'd0;
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dma_waddr_m2 <= 'd0;
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end else begin
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dma_waddr_m1 <= adc_waddr_g;
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dma_waddr_m2 <= dma_waddr_m1;
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end
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dma_waddr <= g2b(dma_waddr_m2);
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dma_addr_diff <= dma_addr_diff_s[5:0];
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if (dma_addr_diff > BUF_THRESHOLD_HI) begin
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dma_almost_full <= 1'b1;
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end else begin
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dma_almost_full <= 1'b0;
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end
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if (dma_addr_diff < BUF_THRESHOLD_LO) begin
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dma_almost_empty <= 1'b1;
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end else begin
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dma_almost_empty <= 1'b0;
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end
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dma_ovf <= dma_ovf_s;
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dma_unf <= dma_unf_s;
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dma_resync <= dma_ovf | dma_unf;
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end
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// adc write- used here to simply transfer data to the dma side
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// address is released with a free running counter
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always @(posedge adc_clk) begin
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adc_wr <= adc_valid;
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if ((adc_resync == 1'b1) || (adc_rst == 1'b1)) begin
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adc_waddr <= 6'd0;
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end else if (adc_wr == 1'b1) begin
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adc_waddr <= adc_waddr + 1'b1;
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end
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adc_waddr_g <= b2g(adc_waddr);
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adc_wdata <= adc_data;
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adc_release_count <= adc_release_count + 1'b1;
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if (adc_release_count == 4'hf) begin
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adc_release_toggle <= ~adc_release_toggle;
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adc_release_waddr <= adc_waddr;
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end
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if (adc_rst == 1'b1) begin
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adc_resync_m1 <= 'd0;
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adc_resync_m2 <= 'd0;
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end else begin
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adc_resync_m1 <= dma_resync;
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adc_resync_m2 <= adc_resync_m1;
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end
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adc_resync <= adc_resync_m2;
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end
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// interface handler for ready
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ad_axis_inf_rx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_inf (
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.clk (dma_clk),
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.rst (dma_rst),
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.valid (dma_valid_int),
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.last (dma_last_int),
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.data (dma_data_int),
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.inf_valid (dma_valid),
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.inf_last (dma_last),
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.inf_data (dma_data),
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.inf_ready (dma_ready));
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// buffer (mainly for clock domain transfer)
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ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem (
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.clka (adc_clk),
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.wea (adc_wr),
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.addra (adc_waddr),
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.dina (adc_wdata),
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.clkb (dma_clk),
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.addrb (dma_raddr),
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.doutb (dma_rdata_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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